forked from dotnet/runtime
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathcodegen.h
1520 lines (1219 loc) · 55.9 KB
/
codegen.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
//
// This class contains all the data & functionality for code generation
// of a method, except for the target-specific elements, which are
// primarily in the Target class.
//
#ifndef _CODEGEN_H_
#define _CODEGEN_H_
#include "codegeninterface.h"
#include "compiler.h" // temporary??
#include "regset.h"
#include "jitgcinfo.h"
class CodeGen final : public CodeGenInterface
{
friend class emitter;
friend class DisAssembler;
public:
// This could use further abstraction
CodeGen(Compiler* theCompiler);
virtual void genGenerateCode(void** codePtr, uint32_t* nativeSizeOfCode);
void genGenerateMachineCode();
void genEmitMachineCode();
void genEmitUnwindDebugGCandEH();
// TODO-Cleanup: Abstract out the part of this that finds the addressing mode, and
// move it to Lower
virtual bool genCreateAddrMode(
GenTree* addr, bool fold, bool* revPtr, GenTree** rv1Ptr, GenTree** rv2Ptr, unsigned* mulPtr, ssize_t* cnsPtr);
private:
#if defined(TARGET_XARCH)
// Bit masks used in negating a float or double number.
// This is to avoid creating more than one data constant for these bitmasks when a
// method has more than one GT_NEG operation on floating point values.
CORINFO_FIELD_HANDLE negBitmaskFlt;
CORINFO_FIELD_HANDLE negBitmaskDbl;
// Bit masks used in computing Math.Abs() of a float or double number.
CORINFO_FIELD_HANDLE absBitmaskFlt;
CORINFO_FIELD_HANDLE absBitmaskDbl;
// Bit mask used in U8 -> double conversion to adjust the result.
CORINFO_FIELD_HANDLE u8ToDblBitmask;
// Generates SSE2 code for the given tree as "Operand BitWiseOp BitMask"
void genSSE2BitwiseOp(GenTree* treeNode);
// Generates SSE41 code for the given tree as a round operation
void genSSE41RoundOp(GenTreeOp* treeNode);
instruction simdAlignedMovIns()
{
// We use movaps when non-VEX because it is a smaller instruction;
// however the VEX version vmovaps would be used which is the same size as vmovdqa;
// also vmovdqa has more available CPU ports on older processors so we switch to that
return compiler->canUseVexEncoding() ? INS_movdqa : INS_movaps;
}
instruction simdUnalignedMovIns()
{
// We use movups when non-VEX because it is a smaller instruction;
// however the VEX version vmovups would be used which is the same size as vmovdqu;
// but vmovdqu has more available CPU ports on older processors so we switch to that
return compiler->canUseVexEncoding() ? INS_movdqu : INS_movups;
}
#endif // defined(TARGET_XARCH)
void genPrepForCompiler();
void genMarkLabelsForCodegen();
inline RegState* regStateForType(var_types t)
{
return varTypeUsesFloatReg(t) ? &floatRegState : &intRegState;
}
inline RegState* regStateForReg(regNumber reg)
{
return genIsValidFloatReg(reg) ? &floatRegState : &intRegState;
}
regNumber genFramePointerReg()
{
if (isFramePointerUsed())
{
return REG_FPBASE;
}
else
{
return REG_SPBASE;
}
}
static bool genShouldRoundFP();
GenTreeIndir indirForm(var_types type, GenTree* base);
GenTreeStoreInd storeIndirForm(var_types type, GenTree* base, GenTree* data);
GenTreeIntCon intForm(var_types type, ssize_t value);
void genRangeCheck(GenTree* node);
void genLockedInstructions(GenTreeOp* node);
#ifdef TARGET_XARCH
void genCodeForLockAdd(GenTreeOp* node);
#endif
#ifdef REG_OPT_RSVD
// On some targets such as the ARM we may need to have an extra reserved register
// that is used when addressing stack based locals and stack based temps.
// This method returns the regNumber that should be used when an extra register
// is needed to access the stack based locals and stack based temps.
//
regNumber rsGetRsvdReg()
{
// We should have already added this register to the mask
// of reserved registers in regSet.rdMaskResvd
noway_assert((regSet.rsMaskResvd & RBM_OPT_RSVD) != 0);
return REG_OPT_RSVD;
}
#endif // REG_OPT_RSVD
//-------------------------------------------------------------------------
bool genUseBlockInit; // true if we plan to block-initialize the local stack frame
unsigned genInitStkLclCnt; // The count of local variables that we need to zero init
void SubtractStackLevel(unsigned adjustment)
{
assert(genStackLevel >= adjustment);
unsigned newStackLevel = genStackLevel - adjustment;
if (genStackLevel != newStackLevel)
{
JITDUMP("Adjusting stack level from %d to %d\n", genStackLevel, newStackLevel);
}
genStackLevel = newStackLevel;
}
void AddStackLevel(unsigned adjustment)
{
unsigned newStackLevel = genStackLevel + adjustment;
if (genStackLevel != newStackLevel)
{
JITDUMP("Adjusting stack level from %d to %d\n", genStackLevel, newStackLevel);
}
genStackLevel = newStackLevel;
}
void SetStackLevel(unsigned newStackLevel)
{
if (genStackLevel != newStackLevel)
{
JITDUMP("Setting stack level from %d to %d\n", genStackLevel, newStackLevel);
}
genStackLevel = newStackLevel;
}
//-------------------------------------------------------------------------
void genReportEH();
// Allocates storage for the GC info, writes the GC info into that storage, records the address of the
// GC info of the method with the EE, and returns a pointer to the "info" portion (just post-header) of
// the GC info. Requires "codeSize" to be the size of the generated code, "prologSize" and "epilogSize"
// to be the sizes of the prolog and epilog, respectively. In DEBUG, makes a check involving the
// "codePtr", assumed to be a pointer to the start of the generated code.
CLANG_FORMAT_COMMENT_ANCHOR;
#ifdef JIT32_GCENCODER
void* genCreateAndStoreGCInfo(unsigned codeSize, unsigned prologSize, unsigned epilogSize DEBUGARG(void* codePtr));
void* genCreateAndStoreGCInfoJIT32(unsigned codeSize,
unsigned prologSize,
unsigned epilogSize DEBUGARG(void* codePtr));
#else // !JIT32_GCENCODER
void genCreateAndStoreGCInfo(unsigned codeSize, unsigned prologSize, unsigned epilogSize DEBUGARG(void* codePtr));
void genCreateAndStoreGCInfoX64(unsigned codeSize, unsigned prologSize DEBUGARG(void* codePtr));
#endif // !JIT32_GCENCODER
/**************************************************************************
* PROTECTED
*************************************************************************/
protected:
// the current (pending) label ref, a label which has been referenced but not yet seen
BasicBlock* genPendingCallLabel;
void** codePtr;
uint32_t* nativeSizeOfCode;
unsigned codeSize;
void* coldCodePtr;
void* consPtr;
#ifdef DEBUG
// Last instr we have displayed for dspInstrs
unsigned genCurDispOffset;
static const char* genInsName(instruction ins);
const char* genInsDisplayName(emitter::instrDesc* id);
static const char* genSizeStr(emitAttr size);
#endif // DEBUG
void genInitialize();
void genInitializeRegisterState();
void genCodeForBBlist();
public:
void genSpillVar(GenTree* tree);
protected:
void genEmitHelperCall(unsigned helper, int argSize, emitAttr retSize, regNumber callTarget = REG_NA);
void genGCWriteBarrier(GenTree* tgt, GCInfo::WriteBarrierForm wbf);
BasicBlock* genCreateTempLabel();
private:
void genLogLabel(BasicBlock* bb);
protected:
void genDefineTempLabel(BasicBlock* label);
void genDefineInlineTempLabel(BasicBlock* label);
void genAdjustSP(target_ssize_t delta);
void genAdjustStackLevel(BasicBlock* block);
void genExitCode(BasicBlock* block);
void genJumpToThrowHlpBlk(emitJumpKind jumpKind, SpecialCodeKind codeKind, BasicBlock* failBlk = nullptr);
void genCheckOverflow(GenTree* tree);
//-------------------------------------------------------------------------
//
// Prolog/epilog generation
//
//-------------------------------------------------------------------------
unsigned prologSize;
unsigned epilogSize;
//
// Prolog functions and data (there are a few exceptions for more generally used things)
//
void genEstablishFramePointer(int delta, bool reportUnwindData);
void genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbered, RegState* regState);
void genEnregisterIncomingStackArgs();
void genCheckUseBlockInit();
#if defined(UNIX_AMD64_ABI) && defined(FEATURE_SIMD)
void genClearStackVec3ArgUpperBits();
#endif // UNIX_AMD64_ABI && FEATURE_SIMD
#if defined(TARGET_ARM64)
bool genInstrWithConstant(instruction ins,
emitAttr attr,
regNumber reg1,
regNumber reg2,
ssize_t imm,
regNumber tmpReg,
bool inUnwindRegion = false);
void genStackPointerAdjustment(ssize_t spAdjustment, regNumber tmpReg, bool* pTmpRegIsZero, bool reportUnwindData);
void genPrologSaveRegPair(regNumber reg1,
regNumber reg2,
int spOffset,
int spDelta,
bool useSaveNextPair,
regNumber tmpReg,
bool* pTmpRegIsZero);
void genPrologSaveReg(regNumber reg1, int spOffset, int spDelta, regNumber tmpReg, bool* pTmpRegIsZero);
void genEpilogRestoreRegPair(regNumber reg1,
regNumber reg2,
int spOffset,
int spDelta,
bool useSaveNextPair,
regNumber tmpReg,
bool* pTmpRegIsZero);
void genEpilogRestoreReg(regNumber reg1, int spOffset, int spDelta, regNumber tmpReg, bool* pTmpRegIsZero);
// A simple struct to keep register pairs for prolog and epilog.
struct RegPair
{
regNumber reg1;
regNumber reg2;
bool useSaveNextPair;
RegPair(regNumber reg1) : reg1(reg1), reg2(REG_NA), useSaveNextPair(false)
{
}
RegPair(regNumber reg1, regNumber reg2) : reg1(reg1), reg2(reg2), useSaveNextPair(false)
{
assert(reg2 == REG_NEXT(reg1));
}
};
static void genBuildRegPairsStack(regMaskTP regsMask, ArrayStack<RegPair>* regStack);
static void genSetUseSaveNextPairs(ArrayStack<RegPair>* regStack);
static int genGetSlotSizeForRegsInMask(regMaskTP regsMask);
void genSaveCalleeSavedRegisterGroup(regMaskTP regsMask, int spDelta, int spOffset);
void genRestoreCalleeSavedRegisterGroup(regMaskTP regsMask, int spDelta, int spOffset);
void genSaveCalleeSavedRegistersHelp(regMaskTP regsToSaveMask, int lowestCalleeSavedOffset, int spDelta);
void genRestoreCalleeSavedRegistersHelp(regMaskTP regsToRestoreMask, int lowestCalleeSavedOffset, int spDelta);
void genPushCalleeSavedRegisters(regNumber initReg, bool* pInitRegZeroed);
#else
void genPushCalleeSavedRegisters();
#endif
void genAllocLclFrame(unsigned frameSize, regNumber initReg, bool* pInitRegZeroed, regMaskTP maskArgRegsLiveIn);
void genPoisonFrame(regMaskTP bbRegLiveIn);
#if defined(TARGET_ARM)
bool genInstrWithConstant(
instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, ssize_t imm, insFlags flags, regNumber tmpReg);
bool genStackPointerAdjustment(ssize_t spAdjustment, regNumber tmpReg);
void genPushFltRegs(regMaskTP regMask);
void genPopFltRegs(regMaskTP regMask);
regMaskTP genStackAllocRegisterMask(unsigned frameSize, regMaskTP maskCalleeSavedFloat);
regMaskTP genJmpCallArgMask();
void genFreeLclFrame(unsigned frameSize,
/* IN OUT */ bool* pUnwindStarted);
void genMov32RelocatableDisplacement(BasicBlock* block, regNumber reg);
void genMov32RelocatableDataLabel(unsigned value, regNumber reg);
void genMov32RelocatableImmediate(emitAttr size, BYTE* addr, regNumber reg);
bool genUsedPopToReturn; // True if we use the pop into PC to return,
// False if we didn't and must branch to LR to return.
// A set of information that is used by funclet prolog and epilog generation. It is collected once, before
// funclet prologs and epilogs are generated, and used by all funclet prologs and epilogs, which must all be the
// same.
struct FuncletFrameInfoDsc
{
regMaskTP fiSaveRegs; // Set of registers saved in the funclet prolog (includes LR)
unsigned fiFunctionCallerSPtoFPdelta; // Delta between caller SP and the frame pointer
unsigned fiSpDelta; // Stack pointer delta
unsigned fiPSP_slot_SP_offset; // PSP slot offset from SP
int fiPSP_slot_CallerSP_offset; // PSP slot offset from Caller SP
};
FuncletFrameInfoDsc genFuncletInfo;
#elif defined(TARGET_ARM64)
// A set of information that is used by funclet prolog and epilog generation. It is collected once, before
// funclet prologs and epilogs are generated, and used by all funclet prologs and epilogs, which must all be the
// same.
struct FuncletFrameInfoDsc
{
regMaskTP fiSaveRegs; // Set of callee-saved registers saved in the funclet prolog (includes LR)
int fiFunction_CallerSP_to_FP_delta; // Delta between caller SP and the frame pointer in the parent function
// (negative)
int fiSP_to_FPLR_save_delta; // FP/LR register save offset from SP (positive)
int fiSP_to_PSP_slot_delta; // PSP slot offset from SP (positive)
int fiSP_to_CalleeSave_delta; // First callee-saved register slot offset from SP (positive)
int fiCallerSP_to_PSP_slot_delta; // PSP slot offset from Caller SP (negative)
int fiFrameType; // Funclet frame types are numbered. See genFuncletProlog() for details.
int fiSpDelta1; // Stack pointer delta 1 (negative)
int fiSpDelta2; // Stack pointer delta 2 (negative)
};
FuncletFrameInfoDsc genFuncletInfo;
#elif defined(TARGET_AMD64)
// A set of information that is used by funclet prolog and epilog generation. It is collected once, before
// funclet prologs and epilogs are generated, and used by all funclet prologs and epilogs, which must all be the
// same.
struct FuncletFrameInfoDsc
{
unsigned fiFunction_InitialSP_to_FP_delta; // Delta between Initial-SP and the frame pointer
unsigned fiSpDelta; // Stack pointer delta
int fiPSP_slot_InitialSP_offset; // PSP slot offset from Initial-SP
};
FuncletFrameInfoDsc genFuncletInfo;
#endif // TARGET_AMD64
#if defined(TARGET_XARCH)
// Save/Restore callee saved float regs to stack
void genPreserveCalleeSavedFltRegs(unsigned lclFrameSize);
void genRestoreCalleeSavedFltRegs(unsigned lclFrameSize);
// Generate VZeroupper instruction to avoid AVX/SSE transition penalty
void genVzeroupperIfNeeded(bool check256bitOnly = true);
#endif // TARGET_XARCH
void genZeroInitFltRegs(const regMaskTP& initFltRegs, const regMaskTP& initDblRegs, const regNumber& initReg);
regNumber genGetZeroReg(regNumber initReg, bool* pInitRegZeroed);
void genZeroInitFrame(int untrLclHi, int untrLclLo, regNumber initReg, bool* pInitRegZeroed);
void genReportGenericContextArg(regNumber initReg, bool* pInitRegZeroed);
void genSetGSSecurityCookie(regNumber initReg, bool* pInitRegZeroed);
void genFinalizeFrame();
#ifdef PROFILING_SUPPORTED
void genProfilingEnterCallback(regNumber initReg, bool* pInitRegZeroed);
void genProfilingLeaveCallback(unsigned helper);
#endif // PROFILING_SUPPORTED
// clang-format off
void genEmitCall(int callType,
CORINFO_METHOD_HANDLE methHnd,
INDEBUG_LDISASM_COMMA(CORINFO_SIG_INFO* sigInfo)
void* addr
X86_ARG(int argSize),
emitAttr retSize
MULTIREG_HAS_SECOND_GC_RET_ONLY_ARG(emitAttr secondRetSize),
IL_OFFSETX ilOffset,
regNumber base,
bool isJump);
// clang-format on
// clang-format off
void genEmitCallIndir(int callType,
CORINFO_METHOD_HANDLE methHnd,
INDEBUG_LDISASM_COMMA(CORINFO_SIG_INFO* sigInfo)
GenTreeIndir* indir
X86_ARG(int argSize),
emitAttr retSize
MULTIREG_HAS_SECOND_GC_RET_ONLY_ARG(emitAttr secondRetSize),
IL_OFFSETX ilOffset,
bool isJump);
// clang-format on
//
// Epilog functions
//
CLANG_FORMAT_COMMENT_ANCHOR;
#if defined(TARGET_ARM)
bool genCanUsePopToReturn(regMaskTP maskPopRegsInt, bool jmpEpilog);
#endif
#if defined(TARGET_ARM64)
void genPopCalleeSavedRegistersAndFreeLclFrame(bool jmpEpilog);
#else // !defined(TARGET_ARM64)
void genPopCalleeSavedRegisters(bool jmpEpilog = false);
#endif // !defined(TARGET_ARM64)
//
// Common or driving functions
//
void genReserveProlog(BasicBlock* block); // currently unused
void genReserveEpilog(BasicBlock* block);
void genFnProlog();
void genFnEpilog(BasicBlock* block);
#if defined(FEATURE_EH_FUNCLETS)
void genReserveFuncletProlog(BasicBlock* block);
void genReserveFuncletEpilog(BasicBlock* block);
void genFuncletProlog(BasicBlock* block);
void genFuncletEpilog();
void genCaptureFuncletPrologEpilogInfo();
void genSetPSPSym(regNumber initReg, bool* pInitRegZeroed);
void genUpdateCurrentFunclet(BasicBlock* block);
#if defined(TARGET_ARM)
void genInsertNopForUnwinder(BasicBlock* block);
#endif
#else // !FEATURE_EH_FUNCLETS
// This is a no-op when there are no funclets!
void genUpdateCurrentFunclet(BasicBlock* block)
{
return;
}
#if defined(TARGET_ARM)
void genInsertNopForUnwinder(BasicBlock* block)
{
return;
}
#endif
#endif // !FEATURE_EH_FUNCLETS
void genGeneratePrologsAndEpilogs();
#if defined(DEBUG) && defined(TARGET_ARM64)
void genArm64EmitterUnitTests();
#endif
#if defined(DEBUG) && defined(LATE_DISASM) && defined(TARGET_AMD64)
void genAmd64EmitterUnitTests();
#endif
#ifdef TARGET_ARM64
virtual void SetSaveFpLrWithAllCalleeSavedRegisters(bool value);
virtual bool IsSaveFpLrWithAllCalleeSavedRegisters() const;
bool genSaveFpLrWithAllCalleeSavedRegisters;
#endif // TARGET_ARM64
//-------------------------------------------------------------------------
//
// End prolog/epilog generation
//
//-------------------------------------------------------------------------
void genSinglePush();
void genSinglePop();
regMaskTP genPushRegs(regMaskTP regs, regMaskTP* byrefRegs, regMaskTP* noRefRegs);
void genPopRegs(regMaskTP regs, regMaskTP byrefRegs, regMaskTP noRefRegs);
/*
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX Debugging Support XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#ifdef DEBUG
void genIPmappingDisp(unsigned mappingNum, Compiler::IPmappingDsc* ipMapping);
void genIPmappingListDisp();
#endif // DEBUG
void genIPmappingAdd(IL_OFFSETX offset, bool isLabel);
void genIPmappingAddToFront(IL_OFFSETX offset);
void genIPmappingGen();
void genEnsureCodeEmitted(IL_OFFSETX offsx);
//-------------------------------------------------------------------------
// scope info for the variables
void genSetScopeInfo(unsigned which,
UNATIVE_OFFSET startOffs,
UNATIVE_OFFSET length,
unsigned varNum,
unsigned LVnum,
bool avail,
siVarLoc* varLoc);
void genSetScopeInfo();
#ifdef USING_VARIABLE_LIVE_RANGE
// Send VariableLiveRanges as debug info to the debugger
void genSetScopeInfoUsingVariableRanges();
#endif // USING_VARIABLE_LIVE_RANGE
#ifdef USING_SCOPE_INFO
void genSetScopeInfoUsingsiScope();
/*
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX ScopeInfo XX
XX XX
XX Keeps track of the scopes during code-generation. XX
XX This is used to translate the local-variable debugging information XX
XX from IL offsets to native code offsets. XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
/*****************************************************************************/
/*****************************************************************************
* ScopeInfo
*
* This class is called during code gen at block-boundaries, and when the
* set of live variables changes. It keeps track of the scope of the variables
* in terms of the native code PC.
*/
#endif // USING_SCOPE_INFO
public:
void siInit();
void checkICodeDebugInfo();
// The logic used to report debug info on debug code is the same for ScopeInfo and
// VariableLiveRange
void siBeginBlock(BasicBlock* block);
void siEndBlock(BasicBlock* block);
// VariableLiveRange and siScope needs this method to report variables on debug code
void siOpenScopesForNonTrackedVars(const BasicBlock* block, unsigned int lastBlockILEndOffset);
protected:
#if defined(FEATURE_EH_FUNCLETS)
bool siInFuncletRegion; // Have we seen the start of the funclet region?
#endif // FEATURE_EH_FUNCLETS
IL_OFFSET siLastEndOffs; // IL offset of the (exclusive) end of the last block processed
#ifdef USING_SCOPE_INFO
public:
// Closes the "ScopeInfo" of the tracked variables that has become dead.
virtual void siUpdate();
void siCheckVarScope(unsigned varNum, IL_OFFSET offs);
void siCloseAllOpenScopes();
#ifdef DEBUG
void siDispOpenScopes();
#endif
/**************************************************************************
* PROTECTED
*************************************************************************/
protected:
struct siScope
{
emitLocation scStartLoc; // emitter location of start of scope
emitLocation scEndLoc; // emitter location of end of scope
unsigned scVarNum; // index into lvaTable
unsigned scLVnum; // 'which' in eeGetLVinfo()
unsigned scStackLevel; // Only for stk-vars
siScope* scPrev;
siScope* scNext;
};
// Returns a "siVarLoc" instance representing the place where the variable lives base on
// varDsc and scope description.
CodeGenInterface::siVarLoc getSiVarLoc(const LclVarDsc* varDsc, const siScope* scope) const;
siScope siOpenScopeList, siScopeList, *siOpenScopeLast, *siScopeLast;
unsigned siScopeCnt;
VARSET_TP siLastLife; // Life at last call to siUpdate()
// Tracks the last entry for each tracked register variable
siScope** siLatestTrackedScopes;
// Functions
siScope* siNewScope(unsigned LVnum, unsigned varNum);
void siRemoveFromOpenScopeList(siScope* scope);
void siEndTrackedScope(unsigned varIndex);
void siEndScope(unsigned varNum);
void siEndScope(siScope* scope);
#ifdef DEBUG
bool siVerifyLocalVarTab();
#endif
#ifdef LATE_DISASM
public:
/* virtual */
const char* siRegVarName(size_t offs, size_t size, unsigned reg);
/* virtual */
const char* siStackVarName(size_t offs, size_t size, unsigned reg, unsigned stkOffs);
#endif // LATE_DISASM
/*
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX PrologScopeInfo XX
XX XX
XX We need special handling in the prolog block, as the parameter variables XX
XX may not be in the same position described by genLclVarTable - they all XX
XX start out on the stack XX
XX XX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
*/
#endif // USING_SCOPE_INFO
public:
void psiBegProlog();
void psiEndProlog();
#ifdef USING_SCOPE_INFO
void psiAdjustStackLevel(unsigned size);
// For EBP-frames, the parameters are accessed via ESP on entry to the function,
// but via EBP right after a "mov ebp,esp" instruction.
void psiMoveESPtoEBP();
// Close previous psiScope and open a new one on the location described by the registers.
void psiMoveToReg(unsigned varNum, regNumber reg = REG_NA, regNumber otherReg = REG_NA);
// Search the open "psiScope" of the "varNum" parameter, close it and open
// a new one using "LclVarDsc" fields.
void psiMoveToStack(unsigned varNum);
/**************************************************************************
* PROTECTED
*************************************************************************/
protected:
struct psiScope
{
emitLocation scStartLoc; // emitter location of start of scope
emitLocation scEndLoc; // emitter location of end of scope
unsigned scSlotNum; // index into lclVarTab
unsigned scLVnum; // 'which' in eeGetLVinfo()
bool scRegister;
union {
struct
{
regNumberSmall scRegNum;
// Used for:
// - "other half" of long var on architectures with 32 bit size registers - x86.
// - for System V structs it stores the second register
// used to pass a register passed struct.
regNumberSmall scOtherReg;
} u1;
struct
{
regNumberSmall scBaseReg;
NATIVE_OFFSET scOffset;
} u2;
};
psiScope* scPrev;
psiScope* scNext;
// Returns a "siVarLoc" instance representing the place where the variable lives base on
// psiScope properties.
CodeGenInterface::siVarLoc getSiVarLoc() const;
};
psiScope psiOpenScopeList, psiScopeList, *psiOpenScopeLast, *psiScopeLast;
unsigned psiScopeCnt;
// Implementation Functions
psiScope* psiNewPrologScope(unsigned LVnum, unsigned slotNum);
void psiEndPrologScope(psiScope* scope);
void psiSetScopeOffset(psiScope* newScope, const LclVarDsc* lclVarDsc) const;
#endif // USING_SCOPE_INFO
NATIVE_OFFSET psiGetVarStackOffset(const LclVarDsc* lclVarDsc) const;
/*****************************************************************************
* TrnslLocalVarInfo
*
* This struct holds the LocalVarInfo in terms of the generated native code
* after a call to genSetScopeInfo()
*/
protected:
#ifdef DEBUG
struct TrnslLocalVarInfo
{
unsigned tlviVarNum;
unsigned tlviLVnum;
VarName tlviName;
UNATIVE_OFFSET tlviStartPC;
size_t tlviLength;
bool tlviAvailable;
siVarLoc tlviVarLoc;
};
// Array of scopes of LocalVars in terms of native code
TrnslLocalVarInfo* genTrnslLocalVarInfo;
unsigned genTrnslLocalVarCount;
#endif
void genSetRegToConst(regNumber targetReg, var_types targetType, GenTree* tree);
void genCodeForTreeNode(GenTree* treeNode);
void genCodeForBinary(GenTreeOp* treeNode);
#if defined(TARGET_X86)
void genCodeForLongUMod(GenTreeOp* node);
#endif // TARGET_X86
void genCodeForDivMod(GenTreeOp* treeNode);
void genCodeForMul(GenTreeOp* treeNode);
void genCodeForIncSaturate(GenTree* treeNode);
void genCodeForMulHi(GenTreeOp* treeNode);
void genLeaInstruction(GenTreeAddrMode* lea);
void genSetRegToCond(regNumber dstReg, GenTree* tree);
#if defined(TARGET_ARMARCH)
void genScaledAdd(emitAttr attr, regNumber targetReg, regNumber baseReg, regNumber indexReg, int scale);
void genCodeForMulLong(GenTreeOp* mul);
#endif // TARGET_ARMARCH
#if !defined(TARGET_64BIT)
void genLongToIntCast(GenTree* treeNode);
#endif
// Generate code for a GT_BITCAST that is not contained.
void genCodeForBitCast(GenTreeOp* treeNode);
// Generate the instruction to move a value between register files
void genBitCast(var_types targetType, regNumber targetReg, var_types srcType, regNumber srcReg);
struct GenIntCastDesc
{
enum CheckKind
{
CHECK_NONE,
CHECK_SMALL_INT_RANGE,
CHECK_POSITIVE,
#ifdef TARGET_64BIT
CHECK_UINT_RANGE,
CHECK_POSITIVE_INT_RANGE,
CHECK_INT_RANGE,
#endif
};
enum ExtendKind
{
COPY,
ZERO_EXTEND_SMALL_INT,
SIGN_EXTEND_SMALL_INT,
#ifdef TARGET_64BIT
ZERO_EXTEND_INT,
SIGN_EXTEND_INT,
#endif
};
private:
CheckKind m_checkKind;
unsigned m_checkSrcSize;
int m_checkSmallIntMin;
int m_checkSmallIntMax;
ExtendKind m_extendKind;
unsigned m_extendSrcSize;
public:
GenIntCastDesc(GenTreeCast* cast);
CheckKind CheckKind() const
{
return m_checkKind;
}
unsigned CheckSrcSize() const
{
assert(m_checkKind != CHECK_NONE);
return m_checkSrcSize;
}
int CheckSmallIntMin() const
{
assert(m_checkKind == CHECK_SMALL_INT_RANGE);
return m_checkSmallIntMin;
}
int CheckSmallIntMax() const
{
assert(m_checkKind == CHECK_SMALL_INT_RANGE);
return m_checkSmallIntMax;
}
ExtendKind ExtendKind() const
{
return m_extendKind;
}
unsigned ExtendSrcSize() const
{
return m_extendSrcSize;
}
};
void genIntCastOverflowCheck(GenTreeCast* cast, const GenIntCastDesc& desc, regNumber reg);
void genIntToIntCast(GenTreeCast* cast);
void genFloatToFloatCast(GenTree* treeNode);
void genFloatToIntCast(GenTree* treeNode);
void genIntToFloatCast(GenTree* treeNode);
void genCkfinite(GenTree* treeNode);
void genCodeForCompare(GenTreeOp* tree);
void genIntrinsic(GenTree* treeNode);
void genPutArgStk(GenTreePutArgStk* treeNode);
void genPutArgReg(GenTreeOp* tree);
#if FEATURE_ARG_SPLIT
void genPutArgSplit(GenTreePutArgSplit* treeNode);
#endif // FEATURE_ARG_SPLIT
#if defined(TARGET_XARCH)
unsigned getBaseVarForPutArgStk(GenTree* treeNode);
#endif // TARGET_XARCH
unsigned getFirstArgWithStackSlot();
void genCompareFloat(GenTree* treeNode);
void genCompareInt(GenTree* treeNode);
#ifdef FEATURE_SIMD
enum SIMDScalarMoveType{
SMT_ZeroInitUpper, // zero initlaize target upper bits
SMT_ZeroInitUpper_SrcHasUpperZeros, // zero initialize target upper bits; source upper bits are known to be zero
SMT_PreserveUpper // preserve target upper bits
};
#ifdef TARGET_ARM64
insOpts genGetSimdInsOpt(emitAttr size, var_types elementType);
#endif
instruction getOpForSIMDIntrinsic(SIMDIntrinsicID intrinsicId, var_types baseType, unsigned* ival = nullptr);
void genSIMDScalarMove(
var_types targetType, var_types type, regNumber target, regNumber src, SIMDScalarMoveType moveType);
void genSIMDZero(var_types targetType, var_types baseType, regNumber targetReg);
void genSIMDIntrinsicInit(GenTreeSIMD* simdNode);
void genSIMDIntrinsicInitN(GenTreeSIMD* simdNode);
void genSIMDIntrinsicUnOp(GenTreeSIMD* simdNode);
void genSIMDIntrinsicBinOp(GenTreeSIMD* simdNode);
void genSIMDIntrinsicRelOp(GenTreeSIMD* simdNode);
void genSIMDIntrinsicShuffleSSE2(GenTreeSIMD* simdNode);
void genSIMDIntrinsicUpperSave(GenTreeSIMD* simdNode);
void genSIMDIntrinsicUpperRestore(GenTreeSIMD* simdNode);
void genSIMDLo64BitConvert(SIMDIntrinsicID intrinsicID,
var_types simdType,
var_types baseType,
regNumber tmpReg,
regNumber tmpIntReg,
regNumber targetReg);
void genSIMDIntrinsic32BitConvert(GenTreeSIMD* simdNode);
void genSIMDIntrinsic64BitConvert(GenTreeSIMD* simdNode);
void genSIMDIntrinsicNarrow(GenTreeSIMD* simdNode);
void genSIMDExtractUpperHalf(GenTreeSIMD* simdNode, regNumber srcReg, regNumber tgtReg);
void genSIMDIntrinsicWiden(GenTreeSIMD* simdNode);
void genSIMDIntrinsic(GenTreeSIMD* simdNode);
// TYP_SIMD12 (i.e Vector3 of size 12 bytes) is not a hardware supported size and requires
// two reads/writes on 64-bit targets. These routines abstract reading/writing of Vector3
// values through an indirection. Note that Vector3 locals allocated on stack would have
// their size rounded to TARGET_POINTER_SIZE (which is 8 bytes on 64-bit targets) and hence
// Vector3 locals could be treated as TYP_SIMD16 while reading/writing.
void genStoreIndTypeSIMD12(GenTree* treeNode);
void genLoadIndTypeSIMD12(GenTree* treeNode);
void genStoreLclTypeSIMD12(GenTree* treeNode);
void genLoadLclTypeSIMD12(GenTree* treeNode);
#ifdef TARGET_X86
void genStoreSIMD12ToStack(regNumber operandReg, regNumber tmpReg);
void genPutArgStkSIMD12(GenTree* treeNode);
#endif // TARGET_X86
#endif // FEATURE_SIMD
#ifdef FEATURE_HW_INTRINSICS
void genHWIntrinsic(GenTreeHWIntrinsic* node);
#if defined(TARGET_XARCH)
void genHWIntrinsic_R_RM(GenTreeHWIntrinsic* node, instruction ins, emitAttr attr, regNumber reg, GenTree* rmOp);
void genHWIntrinsic_R_RM_I(GenTreeHWIntrinsic* node, instruction ins, emitAttr attr, int8_t ival);
void genHWIntrinsic_R_R_RM(GenTreeHWIntrinsic* node, instruction ins, emitAttr attr);
void genHWIntrinsic_R_R_RM(
GenTreeHWIntrinsic* node, instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, GenTree* op2);
void genHWIntrinsic_R_R_RM_I(GenTreeHWIntrinsic* node, instruction ins, emitAttr attr, int8_t ival);
void genHWIntrinsic_R_R_RM_R(GenTreeHWIntrinsic* node, instruction ins, emitAttr attr);
void genHWIntrinsic_R_R_R_RM(