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sashimi-yzhsashimi-yzh
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ready for ics2023
1 parent 6498a76 commit 4bfdb7e

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+66
-408
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25 files changed

+66
-408
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Diff for: ‎Kconfig

+12-10
Original file line numberDiff line numberDiff line change
@@ -2,15 +2,13 @@ mainmenu "NEMU Configuration Menu"
22

33
choice
44
prompt "Base ISA"
5-
default ISA_riscv32
5+
default ISA_riscv
66
config ISA_x86
77
bool "x86"
88
config ISA_mips32
99
bool "mips32"
10-
config ISA_riscv32
11-
bool "riscv32"
12-
config ISA_riscv64
13-
bool "riscv64"
10+
config ISA_riscv
11+
bool "riscv"
1412
config ISA_loongarch32r
1513
bool "loongarch32r"
1614
endchoice
@@ -19,17 +17,21 @@ config ISA
1917
string
2018
default "x86" if ISA_x86
2119
default "mips32" if ISA_mips32
22-
default "riscv32" if ISA_riscv32
23-
default "riscv64" if ISA_riscv64
20+
default "riscv32" if ISA_riscv && !RV64
21+
default "riscv64" if ISA_riscv && RV64
2422
default "loongarch32r" if ISA_loongarch32r
2523
default "none"
2624

2725
config ISA64
28-
depends on ISA_riscv64
26+
depends on ISA_riscv && RV64
2927
bool
3028
default y
3129

3230

31+
if ISA_riscv
32+
source "src/isa/riscv32/Kconfig"
33+
endif
34+
3335
choice
3436
prompt "NEMU execution engine"
3537
default ENGINE_INTERPRETER
@@ -160,13 +162,13 @@ config DIFFTEST
160162

161163
choice
162164
prompt "Reference design"
163-
default DIFFTEST_REF_SPIKE if ISA_riscv64 || ISA_riscv32
165+
default DIFFTEST_REF_SPIKE if ISA_riscv
164166
default DIFFTEST_REF_KVM if ISA_x86
165167
default DIFFTEST_REF_QEMU
166168
depends on DIFFTEST
167169
config DIFFTEST_REF_QEMU
168170
bool "QEMU, communicate with socket"
169-
if ISA_riscv64 || ISA_riscv32
171+
if ISA_riscv
170172
config DIFFTEST_REF_SPIKE
171173
bool "Spike"
172174
endif

Diff for: ‎Makefile

+3-3
Original file line numberDiff line numberDiff line change
@@ -30,13 +30,13 @@ ENGINE ?= $(call remove_quote,$(CONFIG_ENGINE))
3030
NAME = $(GUEST_ISA)-nemu-$(ENGINE)
3131

3232
# Include all filelist.mk to merge file lists
33-
FILELIST_MK = $(shell find ./src -name "filelist.mk")
33+
FILELIST_MK = $(shell find -L ./src -name "filelist.mk")
3434
include $(FILELIST_MK)
3535

3636
# Filter out directories and files in blacklist to obtain the final set of source files
3737
DIRS-BLACKLIST-y += $(DIRS-BLACKLIST)
38-
SRCS-BLACKLIST-y += $(SRCS-BLACKLIST) $(shell find $(DIRS-BLACKLIST-y) -name "*.c")
39-
SRCS-y += $(shell find $(DIRS-y) -name "*.c")
38+
SRCS-BLACKLIST-y += $(SRCS-BLACKLIST) $(shell find -L $(DIRS-BLACKLIST-y) -name "*.c")
39+
SRCS-y += $(shell find -L $(DIRS-y) -name "*.c")
4040
SRCS = $(filter-out $(SRCS-BLACKLIST-y),$(SRCS-y))
4141

4242
# Extract compiler and options from menuconfig

Diff for: ‎include/difftest-def.h

+5-4
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#define __DIFFTEST_DEF_H__
1818

1919
#include <stdint.h>
20+
#include <macro.h>
2021
#include <generated/autoconf.h>
2122

2223
#define __EXPORT __attribute__((visibility("default")))
@@ -26,10 +27,10 @@ enum { DIFFTEST_TO_DUT, DIFFTEST_TO_REF };
2627
# define DIFFTEST_REG_SIZE (sizeof(uint32_t) * 9) // GPRs + pc
2728
#elif defined(CONFIG_ISA_mips32)
2829
# define DIFFTEST_REG_SIZE (sizeof(uint32_t) * 38) // GPRs + status + lo + hi + badvaddr + cause + pc
29-
#elif defined(CONFIG_ISA_riscv32)
30-
# define DIFFTEST_REG_SIZE (sizeof(uint32_t) * 33) // GPRs + pc
31-
#elif defined(CONFIG_ISA_riscv64)
32-
# define DIFFTEST_REG_SIZE (sizeof(uint64_t) * 33) // GPRs + pc
30+
#elif defined(CONFIG_ISA_riscv)
31+
#define RISCV_GPR_TYPE MUXDEF(CONFIG_RV64, uint64_t, uint32_t)
32+
#define RISCV_GPR_NUM MUXDEF(CONFIG_RVE , 16, 32)
33+
#define DIFFTEST_REG_SIZE (sizeof(RISCV_GPR_TYPE) * (RISCV_GPR_NUM + 1)) // GPRs + pc
3334
#elif defined(CONFIG_ISA_loongarch32r)
3435
# define DIFFTEST_REG_SIZE (sizeof(uint32_t) * 33) // GPRs + pc
3536
#else

Diff for: ‎include/isa.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ typedef concat(__GUEST_ISA__, _CPU_state) CPU_state;
2525
typedef concat(__GUEST_ISA__, _ISADecodeInfo) ISADecodeInfo;
2626

2727
// monitor
28-
extern char isa_logo[];
28+
extern unsigned char isa_logo[];
2929
void init_isa();
3030

3131
// reg

Diff for: ‎src/isa/loongarch32r/local-include/reg.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ static inline int check_reg_idx(int idx) {
2525

2626
#define gpr(idx) cpu.gpr[check_reg_idx(idx)]
2727

28-
static inline const char* reg_name(int idx, int width) {
28+
static inline const char* reg_name(int idx) {
2929
extern const char* regs[];
3030
return regs[check_reg_idx(idx)];
3131
}

Diff for: ‎src/isa/mips32/local-include/reg.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ static inline int check_reg_idx(int idx) {
2525

2626
#define gpr(idx) cpu.gpr[check_reg_idx(idx)]
2727

28-
static inline const char* reg_name(int idx, int width) {
28+
static inline const char* reg_name(int idx) {
2929
extern const char* regs[];
3030
return regs[check_reg_idx(idx)];
3131
}

Diff for: ‎src/isa/riscv32/Kconfig

+10
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
menu "ISA-dependent Options for riscv"
2+
3+
config RV64
4+
bool "64-bit RISC-V architecture"
5+
default n
6+
7+
config RVE
8+
bool "Use E extension"
9+
default n
10+
endmenu

Diff for: ‎src/isa/riscv32/include/isa-def.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -13,22 +13,22 @@
1313
* See the Mulan PSL v2 for more details.
1414
***************************************************************************************/
1515

16-
#ifndef __ISA_RISCV32_H__
17-
#define __ISA_RISCV32_H__
16+
#ifndef __ISA_RISCV_H__
17+
#define __ISA_RISCV_H__
1818

1919
#include <common.h>
2020

2121
typedef struct {
22-
word_t gpr[32];
22+
word_t gpr[MUXDEF(CONFIG_RVE, 16, 32)];
2323
vaddr_t pc;
24-
} riscv32_CPU_state;
24+
} MUXDEF(CONFIG_RV64, riscv64_CPU_state, riscv32_CPU_state);
2525

2626
// decode
2727
typedef struct {
2828
union {
2929
uint32_t val;
3030
} inst;
31-
} riscv32_ISADecodeInfo;
31+
} MUXDEF(CONFIG_RV64, riscv64_ISADecodeInfo, riscv32_ISADecodeInfo);
3232

3333
#define isa_mmu_check(vaddr, len, type) (MMU_DIRECT)
3434

Diff for: ‎src/isa/riscv32/init.c

+4-3
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,11 @@
1919
// this is not consistent with uint8_t
2020
// but it is ok since we do not access the array directly
2121
static const uint32_t img [] = {
22-
0x800002b7, // lui t0,0x80000
23-
0x0002a023, // sw zero,0(t0)
24-
0x0002a503, // lw a0,0(t0)
22+
0x00000297, // auipc t0,0
23+
0x00028823, // sb zero,16(t0)
24+
0x0102c503, // lbu a0,16(t0)
2525
0x00100073, // ebreak (used as nemu_trap)
26+
0xdeadbeef, // some data
2627
};
2728

2829
static void restart() {

Diff for: ‎src/isa/riscv32/inst.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -57,9 +57,9 @@ static int decode_exec(Decode *s) {
5757
}
5858

5959
INSTPAT_START();
60-
INSTPAT("??????? ????? ????? ??? ????? 01101 11", lui , U, R(rd) = imm);
61-
INSTPAT("??????? ????? ????? 010 ????? 00000 11", lw , I, R(rd) = Mr(src1 + imm, 4));
62-
INSTPAT("??????? ????? ????? 010 ????? 01000 11", sw , S, Mw(src1 + imm, 4, src2));
60+
INSTPAT("??????? ????? ????? ??? ????? 00101 11", auipc , U, R(rd) = s->pc + imm);
61+
INSTPAT("??????? ????? ????? 100 ????? 00000 11", lbu , I, R(rd) = Mr(src1 + imm, 1));
62+
INSTPAT("??????? ????? ????? 000 ????? 01000 11", sb , S, Mw(src1 + imm, 1, src2));
6363

6464
INSTPAT("0000000 00001 00000 000 00000 11100 11", ebreak , N, NEMUTRAP(s->pc, R(10))); // R(10) is $a0
6565
INSTPAT("??????? ????? ????? ??? ????? ????? ??", inv , N, INV(s->pc));

Diff for: ‎src/isa/riscv32/local-include/reg.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -13,19 +13,19 @@
1313
* See the Mulan PSL v2 for more details.
1414
***************************************************************************************/
1515

16-
#ifndef __RISCV32_REG_H__
17-
#define __RISCV32_REG_H__
16+
#ifndef __RISCV_REG_H__
17+
#define __RISCV_REG_H__
1818

1919
#include <common.h>
2020

2121
static inline int check_reg_idx(int idx) {
22-
IFDEF(CONFIG_RT_CHECK, assert(idx >= 0 && idx < 32));
22+
IFDEF(CONFIG_RT_CHECK, assert(idx >= 0 && idx < MUXDEF(CONFIG_RVE, 16, 32)));
2323
return idx;
2424
}
2525

26-
#define gpr(idx) cpu.gpr[check_reg_idx(idx)]
26+
#define gpr(idx) (cpu.gpr[check_reg_idx(idx)])
2727

28-
static inline const char* reg_name(int idx, int width) {
28+
static inline const char* reg_name(int idx) {
2929
extern const char* regs[];
3030
return regs[check_reg_idx(idx)];
3131
}

Diff for: ‎src/isa/riscv32/system/mmu.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,8 @@
1414
***************************************************************************************/
1515

1616
#include <isa.h>
17-
#include <memory/paddr.h>
1817
#include <memory/vaddr.h>
18+
#include <memory/paddr.h>
1919

2020
paddr_t isa_mmu_translate(vaddr_t vaddr, int len, int type) {
2121
return MEM_RET_FAIL;

Diff for: ‎src/isa/riscv64

+1
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
riscv32

Diff for: ‎src/isa/riscv64/difftest/dut.c

-25
This file was deleted.

Diff for: ‎src/isa/riscv64/include/isa-def.h

-35
This file was deleted.

Diff for: ‎src/isa/riscv64/init.c

-43
This file was deleted.

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