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Copy pathperfmon_sapphirerapids_events.txt
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perfmon_sapphirerapids_events.txt
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# =======================================================================================
#
# Filename: perfmon_sapphirerapids_events.txt
#
# Description: Event list for Intel Sapphire Rapids
#
# Version: <VERSION>
# Released: <DATE>
#
# Author: Thomas Gruber (tr), [email protected]
# Project: likwid
#
# Copyright (C) 2016 RRZE, University Erlangen-Nuremberg
#
# This program is free software: you can redistribute it and/or modify it under
# the terms of the GNU General Public License as published by the Free Software
# Foundation, either version 3 of the License, or (at your option) any later
# version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
# PARTICULAR PURPOSE. See the GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along with
# this program. If not, see <http://www.gnu.org/licenses/>.
#
# =======================================================================================
EVENT_TEMP_CORE 0x00 TMP0
UMASK_TEMP_CORE 0x00
EVENT_PWR_PKG_ENERGY 0x02 PWR0
UMASK_PWR_PKG_ENERGY 0x00
EVENT_PWR_PP0_ENERGY 0x01 PWR1
UMASK_PWR_PP0_ENERGY 0x00
EVENT_PWR_PP1_ENERGY 0x04 PWR2
UMASK_PWR_PP1_ENERGY 0x00
EVENT_PWR_DRAM_ENERGY 0x03 PWR3
UMASK_PWR_DRAM_ENERGY 0x00
EVENT_PWR_PLATFORM_ENERGY 0x05 PWR4
UMASK_PWR_PLATFORM_ENERGY 0x00
EVENT_VOLTAGE_CORE 0x00 VTG0
UMASK_VOLTAGE_CORE 0x00
EVENT_INSTR_RETIRED 0x00 FIXC0
UMASK_INSTR_RETIRED_ANY 0x01
EVENT_CPU_CLK_UNHALTED_CORE 0x00 FIXC1
UMASK_CPU_CLK_UNHALTED_CORE 0x02
EVENT_CPU_CLK_UNHALTED_REF 0x00 FIXC2
UMASK_CPU_CLK_UNHALTED_REF 0x03
EVENT_TOPDOWN_SLOTS 0x00 FIXC3
UMASK_TOPDOWN_SLOTS 0x04
EVENT_RETIRING 0x00 TMA0
UMASK_RETIRING 0x00
EVENT_BAD_SPECULATION 0x00 TMA1
UMASK_BAD_SPECULATION 0x00
EVENT_FRONTEND_BOUND 0x00 TMA2
UMASK_FRONTEND_BOUND 0x00
EVENT_BACKEND_BOUND 0x00 TMA3
UMASK_BACKEND_BOUND 0x00
EVENT_LD_BLOCKS 0x03 PMC
UMASK_LD_BLOCKS_ADDRESS_ALIAS 0x04
UMASK_LD_BLOCKS_STORE_FORWARD 0x82
UMASK_LD_BLOCKS_NO_SR 0x88
EVENT_ITLB_MISSES 0x11 PMC
UMASK_ITLB_MISSES_WALK_COMPLETED_4K 0x02
UMASK_ITLB_MISSES_WALK_COMPLETED_2M_4M 0x04
#UMASK_ITLB_MISSES_WALK_COMPLETED_1G 0x08
UMASK_ITLB_MISSES_WALK_COMPLETED 0x0E
UMASK_ITLB_MISSES_WALK_PENDING 0x10
UMASK_ITLB_MISSES_STLB_HIT 0x20
EVENT_DTLB_LOAD_MISSES 0x12 PMC
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_4K 0x02
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_2M_4M 0x04
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_1G 0x08
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED 0x0E
DEFAULT_OPTIONS_DTLB_LOAD_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_DTLB_LOAD_MISSES_WALK_ACTIVE 0x10
UMASK_DTLB_LOAD_MISSES_WALK_PENDING 0x10
UMASK_DTLB_LOAD_MISSES_STLB_HIT 0x20
EVENT_DTLB_STORE_MISSES 0x13 PMC
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_4K 0x02
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_2M_4M 0x04
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_1G 0x08
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED 0x0E
DEFAULT_OPTIONS_DTLB_STORE_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_DTLB_STORE_MISSES_WALK_ACTIVE 0x10
UMASK_DTLB_STORE_MISSES_WALK_PENDING 0x10
UMASK_DTLB_STORE_MISSES_STLB_HIT 0x20
EVENT_OFFCORE_REQUESTS_OUTSTANDING 0x20 PMC
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO 0x04
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD 0x08
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DATA_RD 0x08
EVENT_OFFCORE_REQUESTS 0x21 PMC
UMASK_OFFCORE_REQUESTS_DEMAND_DATA_RD 0x01
UMASK_OFFCORE_REQUESTS_DATA_RD 0x08
UMASK_OFFCORE_REQUESTS_ALL_REQUESTS 0x80
EVENT_L2_RQSTS 0x24 PMC
UMASK_L2_RQSTS_DEMAND_DATA_RD_MISS 0x21
UMASK_L2_RQSTS_RFO_MISS 0x22
UMASK_L2_RQSTS_CODE_RD_MISS 0x24
UMASK_L2_RQSTS_ALL_DEMAND_MISS 0x27
UMASK_L2_RQSTS_SWPF_MISS 0x28
UMASK_L2_RQSTS_DEMAND_DATA_RD_HIT 0xC1
UMASK_L2_RQSTS_RFO_HIT 0xC2
UMASK_L2_RQSTS_CODE_RD_HIT 0xC4
UMASK_L2_RQSTS_SWPF_HIT 0xC8
UMASK_L2_RQSTS_ALL_DEMAND_DATA_RD 0xE1
UMASK_L2_RQSTS_ALL_RFO 0xE2
UMASK_L2_RQSTS_ALL_CODE_RD 0xE4
UMASK_L2_RQSTS_ALL_DEMAND_REFERENCES 0xE7
UMASK_L2_RQSTS_MISS 0x3F
UMASK_L2_RQSTS_REFERENCES 0xFF
EVENT_L2_REQUEST 0x24 PMC
UMASK_L2_REQUEST_MISS 0x3F
UMASK_L2_REQUEST_ALL 0xFF
EVENT_L2_LINES_IN 0x25 PMC
UMASK_L2_LINES_IN_ALL 0x1F
EVENT_L2_LINES_OUT 0x26 PMC
UMASK_L2_LINES_OUT_SILENT 0x01
UMASK_L2_LINES_OUT_NON_SILENT 0x02
#UMASK_L2_LINES_OUT_USELESS_HWPF 0x04
EVENT_XQ_FULL_CYCLES 0x2D PMC
DEFAULT_OPTIONS_XQ_FULL_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_XQ_FULL_CYCLES 0x01
EVENT_LONGEST_LAT_CACHE 0x2E PMC
UMASK_LONGEST_LAT_CACHE_MISS 0x41
#UMASK_LONGEST_LAT_CACHE_REFERENCE 0x4F
EVENT_CPU_CLOCK_UNHALTED 0x3C PMC
UMASK_CPU_CLOCK_UNHALTED_THREAD_P 0x00
UMASK_CPU_CLOCK_UNHALTED_REF_XCLK 0x01
UMASK_CPU_CLOCK_UNHALTED_ONE_THREAD_ACTIVE 0x02
UMASK_CPU_CLOCK_UNHALTED_REF_DISTRIBUTED 0x08
# Added by Thomas Gruber: Idea is to count also in halted state
DEFAULT_OPTIONS_CPU_CLOCK_UNHALTED_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1
UMASK_CPU_CLOCK_UNHALTED_TOTAL_CYCLES 0x00
EVENT_SW_PREFETCH_ACCESS 0x40 PMC
UMASK_SW_PREFETCH_ACCESS_NTA 0x01
UMASK_SW_PREFETCH_ACCESS_T0 0x02
UMASK_SW_PREFETCH_ACCESS_T1_T2 0x04
UMASK_SW_PREFETCH_ACCESS_PREFETCHW 0x08
EVENT_MEM_LOAD_COMPLETED 0x43 PMC
UMASK_MEM_LOAD_COMPLETED_L1_MISS_ANY 0xFD
EVENT_MEM_STORE_RETIRED 0x44 PMC
UMASK_MEM_STORE_RETIRED_L2_HIT 0x01
EVENT_MEMORY_ACTIVITY 0x47 PMC
DEFAULT_OPTIONS_MEMORY_ACTIVITY_CYCLES_L1D_MISS EVENT_OPTION_THRESHOLD=0x2
UMASK_MEMORY_ACTIVITY_CYCLES_L1D_MISS 0x02
DEFAULT_OPTIONS_MEMORY_ACTIVITY_STALLS_L1D_MISS EVENT_OPTION_THRESHOLD=0x3
UMASK_MEMORY_ACTIVITY_STALLS_L1D_MISS 0x03
DEFAULT_OPTIONS_MEMORY_ACTIVITY_STALLS_L2_MISS EVENT_OPTION_THRESHOLD=0x5
UMASK_MEMORY_ACTIVITY_STALLS_L2_MISS 0x05
DEFAULT_OPTIONS_MEMORY_ACTIVITY_STALLS_L3_MISS EVENT_OPTION_THRESHOLD=0x9
UMASK_MEMORY_ACTIVITY_STALLS_L3_MISS 0x09
EVENT_L1D_PEND_MISS 0x48 PMC
UMASK_L1D_PEND_MISS_PENDING 0x01
DEFAULT_OPTIONS_L1D_PEND_MISS_PENDING_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_L1D_PEND_MISS_PENDING_CYCLES 0x01
UMASK_L1D_PEND_MISS_FB_FULL 0x02
DEFAULT_OPTIONS_L1D_PEND_MISS_FB_FULL_PERIODS EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=0x1
UMASK_L1D_PEND_MISS_FB_FULL_PERIODS 0x02
UMASK_L1D_PEND_MISS_L2_STALLS 0x04
EVENT_LOAD_HIT_PREFETCH 0x4C PMC
UMASK_LOAD_HIT_PREFETCH_SWPF 0x01
EVENT_L1D_REPLACEMENT 0x51 PMC
UMASK_L1D_REPLACEMENT 0x01
EVENT_TX_MEM 0x54 PMC
UMASK_TX_MEM_ABORT_CONFLICT 0x01
UMASK_TX_MEM_ABORT_CAPACITY_WRITE 0x02
UMASK_TX_MEM_ABORT_CAPACITY_READ 0x80
EVENT_DSB2MITE_SWITCHES 0x61 PMC
UMASK_DSB2MITE_SWITCHES_PENALTY_CYCLES 0x02
EVENT_INST_DECODED_DECODERS 0x75 PMC
UMASK_INST_DECODED_DECODERS 0x01
EVENT_UOPS_DECODED_DEC0_UOPS 0x76 PMC
UMASK_UOPS_DECODED_DEC0_UOPS 0x01
EVENT_IDQ 0x79 PMC
UMASK_IDQ_MITE_UOPS 0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MITE_CYCLES_ANY 0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_OK EVENT_OPTION_THRESHOLD=0x6
UMASK_IDQ_MITE_CYCLES_OK 0x04
UMASK_IDQ_DSB_UOPS 0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_DSB_CYCLES_ANY 0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_OK EVENT_OPTION_THRESHOLD=0x6
UMASK_IDQ_DSB_CYCLES_OK 0x08
UMASK_IDQ_MS_UOPS 0x20
DEFAULT_OPTIONS_IDQ_MS_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MS_CYCLES_ANY 0x20
DEFAULT_OPTIONS_IDQ_MS_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=0x1
UMASK_IDQ_MS_SWITCHES 0x20
EVENT_ICACHE_DATA 0x80 PMC
UMASK_ICACHE_DATA_STALLS 0x04
EVENT_ICACHE_TAG 0x83 PMC
UMASK_ICACHE_TAG_STALLS 0x04
EVENT_DECODE_LCP 0x87 PMC
UMASK_DECODE_LCP 0x01
EVENT_IDQ_UOPS_NOT_DELIVERED 0x9C PMC
UMASK_IDQ_UOPS_NOT_DELIVERED_CORE 0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE EVENT_OPTION_THRESHOLD=0x6
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE 0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=0x1
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK 0x01
EVENT_RESOURCE_STALLS 0xA2 PMC
UMASK_RESOURCE_STALLS_SCOREBOARD 0x02
UMASK_RESOURCE_STALLS_SB 0x08
EVENT_CYCLE_ACTIVITY 0xA3 PMC
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L1D_MISS EVENT_OPTION_THRESHOLD=0x8
UMASK_CYCLE_ACTIVITY_CYCLES_L1D_MISS 0x08
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L2_MISS EVENT_OPTION_THRESHOLD=0x1
UMASK_CYCLE_ACTIVITY_CYCLES_L2_MISS 0x01
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L3_MISS EVENT_OPTION_THRESHOLD=0x2
UMASK_CYCLE_ACTIVITY_CYCLES_L3_MISS 0x02
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_MEM_ANY EVENT_OPTION_THRESHOLD=0x10
UMASK_CYCLE_ACTIVITY_CYCLES_MEM_ANY 0x10
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_NO_EXECUTE EVENT_OPTION_THRESHOLD=0x04
UMASK_CYCLE_ACTIVITY_CYCLES_NO_EXECUTE 0x04
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_TOTAL EVENT_OPTION_THRESHOLD=0x4
UMASK_CYCLE_ACTIVITY_STALLS_TOTAL 0x04
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L1D_MISS EVENT_OPTION_THRESHOLD=0xC
UMASK_CYCLE_ACTIVITY_STALLS_L1D_MISS 0x0C
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L2_MISS EVENT_OPTION_THRESHOLD=0x5
UMASK_CYCLE_ACTIVITY_STALLS_L2_MISS 0x05
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L3_MISS EVENT_OPTION_THRESHOLD=0x6
UMASK_CYCLE_ACTIVITY_STALLS_L3_MISS 0x06
#DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_MEM_ANY EVENT_OPTION_THRESHOLD=0x14
#UMASK_CYCLE_ACTIVITY_STALLS_MEM_ANY 0x14
EVENT_TOPDOWN 0xA4 PMC
UMASK_TOPDOWN_SLOTS_P 0x01
UMASK_TOPDOWN_BACKEND_BOUND_SLOTS 0x02
UMASK_TOPDOWN_BAD_SPEC_SLOTS 0x04
UMASK_TOPDOWN_BR_MISPREDICT_SLOTS 0x08
UMASK_TOPDOWN_MEMORY_BOUND_SLOTS 0x10
EVENT_RS_EMPTY_CYCLES 0xA5 PMC
UMASK_RS_EMPTY_CYCLES 0x07
EVENT_EXE_ACTIVITY 0xA6 PMC
UMASK_EXE_ACTIVITY_1_PORTS_UTIL 0x02
UMASK_EXE_ACTIVITY_2_PORTS_UTIL 0x04
UMASK_EXE_ACTIVITY_3_PORTS_UTIL 0x08
UMASK_EXE_ACTIVITY_4_PORTS_UTIL 0x10
DEFAULT_OPTIONS_EXE_ACTIVITY_BOUND_ON_LOADS EVENT_OPTION_THRESHOLD=0x5
UMASK_EXE_ACTIVITY_BOUND_ON_LOADS 0x21
DEFAULT_OPTIONS_EXE_ACTIVITY_BOUND_ON_STORES EVENT_OPTION_THRESHOLD=0x2
UMASK_EXE_ACTIVITY_BOUND_ON_STORES 0x40
EVENT_LSD 0xA8 PMC
UMASK_LSD_UOPS 0x01
DEFAULT_OPTIONS_LSD_CYCLES_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_LSD_CYCLES_ACTIVE 0x01
DEFAULT_OPTIONS_LSD_CYCLES_OK EVENT_OPTION_THRESHOLD=0x6
UMASK_LSD_CYCLES_OK 0x01
EVENT_INT_MISC 0xAD PMC
UMASK_INT_MISC_RECOVERY_CYCLES 0x01
UMASK_INT_MISC_UOP_DROPPING 0x10
UMASK_INT_MISC_MBA_STALLS 0x20
# Needs separate MSR 0x3F7 (content 0x7) and must be counted alone
#UMASK_INT_MISC_UNKNOWN_BRANCH_CYCLES 0x40
UMASK_INT_MISC_CLEAR_RESTEER_CYCLES 0x80
EVENT_UOPS_ISSUED_ANY 0xAE PMC
UMASK_UOPS_ISSUED_ANY 0x01
EVENT_ARITH 0xB0 PMC
DEFAULT_OPTIONS_ARITH_FP_DIVIDER_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_ARITH_FP_DIVIDER_ACTIVE 0x01
DEFAULT_OPTIONS_ARITH_FPDIV_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_ARITH_FPDIV_ACTIVE 0x01
DEFAULT_OPTIONS_ARITH_INT_DIVIDER_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_ARITH_INT_DIVIDER_ACTIVE 0x08
DEFAULT_OPTIONS_ARITH_IDIV_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_ARITH_IDIV_ACTIVE 0x08
DEFAULT_OPTIONS_ARITH_DIVIDER_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_ARITH_DIVIDER_ACTIVE 0x09
DEFAULT_OPTIONS_ARITH_DIV_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_ARITH_DIV_ACTIVE 0x09
# Added by Thomas Gruber to count instructions
DEFAULT_OPTIONS_ARITH_FPDIV_COUNT EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=0x1
UMASK_ARITH_FPDIV_COUNT 0x01
DEFAULT_OPTIONS_ARITH_IDIV_COUNT EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=0x1
UMASK_ARITH_IDIV_COUNT 0x08
DEFAULT_OPTIONS_ARITH_DIV_COUNT EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=0x1
UMASK_ARITH_DIV_COUNT 0x09
EVENT_UOPS_EXECUTED 0xB1 PMC
UMASK_UOPS_EXECUTED_THREAD 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_EXECUTED_STALL_CYCLES 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_STALLS EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_EXECUTED_STALLS 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_1 EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_EXECUTED_CYCLES_GE_1 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_2 EVENT_OPTION_THRESHOLD=0x2
UMASK_UOPS_EXECUTED_CYCLES_GE_2 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_3 EVENT_OPTION_THRESHOLD=0x3
UMASK_UOPS_EXECUTED_CYCLES_GE_3 0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_4 EVENT_OPTION_THRESHOLD=0x4
UMASK_UOPS_EXECUTED_CYCLES_GE_4 0x01
UMASK_UOPS_EXECUTED_CORE 0x02
#DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
#UMASK_UOPS_EXECUTED_CORE_STALL_CYCLES 0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_1 EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_1 0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_2 EVENT_OPTION_THRESHOLD=0x2
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_2 0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_3 EVENT_OPTION_THRESHOLD=0x3
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_3 0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_4 EVENT_OPTION_THRESHOLD=0x4
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_4 0x02
UMASK_UOPS_EXECUTED_X87 0x10
EVENT_UOPS_DISPATCHED 0xB2 PMC
UMASK_UOPS_DISPATCHED_PORT_PORT_0 0x01
UMASK_UOPS_DISPATCHED_PORT_PORT_1 0x02
UMASK_UOPS_DISPATCHED_PORT_PORT_2_3_10 0x04
UMASK_UOPS_DISPATCHED_PORT_PORT_4_9 0x10
UMASK_UOPS_DISPATCHED_PORT_PORT_5_11 0x20
UMASK_UOPS_DISPATCHED_PORT_PORT_6 0x40
UMASK_UOPS_DISPATCHED_PORT_PORT_7_8 0x80
EVENT_FP_ARITH_DISPATCHED 0xB3 PMC
UMASK_FP_ARITH_DISPATCHED_PORT_0 0x01
UMASK_FP_ARITH_DISPATCHED_PORT_1 0x02
UMASK_FP_ARITH_DISPATCHED_PORT_5 0x04
EVENT_EXE_AMX_BUSY 0xB7 PMC
UMASK_EXE_AMX_BUSY 0x02
EVENT_INST_RETIRED 0xC0 PMC
UMASK_INST_RETIRED_ANY 0x00
UMASK_INST_RETIRED_ANY_P 0x00
UMASK_INST_RETIRED_NOP 0x02
UMASK_INST_RETIRED_REP_ITERATION 0x08
UMASK_INST_RETIRED_MACRO_FUSED 0x10
EVENT_ASSISTS 0xC1 PMC
UMASK_ASSISTS_FP 0x02
UMASK_ASSISTS_PAGE_FAULT 0x08
UMASK_ASSISTS_SSE_AVX_MIX 0x10
UMASK_ASSISTS_ANY 0x1F
EVENT_UOPS_RETIRED 0xC2 PMC
UMASK_UOPS_RETIRED_HEAVY 0x01
UMASK_UOPS_RETIRED_SLOTS 0x02
DEFAULT_OPTIONS_UOPS_RETIRED_STALL_CYCLES EVENT_OPTION_INVERT=0x1,EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_RETIRED_STALL_CYCLES 0x02
DEFAULT_OPTIONS_UOPS_RETIRED_STALLS EVENT_OPTION_INVERT=0x1,EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_RETIRED_STALLS 0x02
DEFAULT_OPTIONS_UOPS_RETIRED_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_RETIRED_CYCLES 0x02
# Has to be measured as only event. There is currently no logic for that in LIKWID
#UMASK_UOPS_RETIRED_MS 0x04
EVENT_MACHINE_CLEARS 0xC3 PMC
DEFAULT_OPTIONS_MACHINE_CLEARS_COUNT EVENT_OPTION_EDGE=0x1,EVENT_OPTION_THRESHOLD=0x1
UMASK_MACHINE_CLEARS_COUNT 0x01
UMASK_MACHINE_CLEARS_MEMORY_ORDERING 0x02
UMASK_MACHINE_CLEARS_SMC 0x04
EVENT_BR_INST_RETIRED 0xC4 PMC
UMASK_BR_INST_RETIRED_ALL_BRANCHES 0x00
UMASK_BR_INST_RETIRED_COND_TAKEN 0x01
UMASK_BR_INST_RETIRED_NEAR_CALL 0x02
UMASK_BR_INST_RETIRED_NEAR_RETURN 0x08
UMASK_BR_INST_RETIRED_COND_NTAKEN 0x10
UMASK_BR_INST_RETIRED_COND 0x11
UMASK_BR_INST_RETIRED_NEAR_TAKEN 0x20
UMASK_BR_INST_RETIRED_FAR_BRANCH 0x40
UMASK_BR_INST_RETIRED_INDIRECT 0x80
EVENT_BR_MISP_RETIRED 0xC5 PMC
UMASK_BR_MISP_RETIRED_ALL_BRANCHES 0x00
UMASK_BR_MISP_RETIRED_COND_TAKEN 0x01
UMASK_BR_MISP_RETIRED_INDIRECT_CALL 0x02
UMASK_BR_MISP_RETIRED_RET 0x08
UMASK_BR_MISP_RETIRED_COND_NTAKEN 0x10
UMASK_BR_MISP_RETIRED_COND 0x11
UMASK_BR_MISP_RETIRED_NEAR_TAKEN 0x20
UMASK_BR_MISP_RETIRED_INDIRECT 0x80
# Requires register 0x3F7 (assuming match0) and all must be taken as alone measurement
#EVENT_FRONTEND_RETIRED 0xC6 PMC
#DEFAULT_OPTIONS_FRONTEND_RETIRED_DSB_MISS EVENT_OPTION_MATCH0=0x11
#UMASK_FRONTEND_RETIRED_DSB_MISS 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_ITLB_MISS EVENT_OPTION_MATCH0=0x14
#UMASK_FRONTEND_RETIRED_ITLB_MISS 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_L1I_MISS EVENT_OPTION_MATCH0=0x12
#UMASK_FRONTEND_RETIRED_L1I_MISS 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_L2_MISS EVENT_OPTION_MATCH0=0x13
#UMASK_FRONTEND_RETIRED_L2_MISS 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_STLB_MISS EVENT_OPTION_MATCH0=0x15
#UMASK_FRONTEND_RETIRED_STLB_MISS 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_UNKNOWN_BRANCH EVENT_OPTION_MATCH0=0x17
#UMASK_FRONTEND_RETIRED_UNKNOWN_BRANCH 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_MS_FLOWS EVENT_OPTION_MATCH0=0x8
#UMASK_FRONTEND_RETIRED_MS_FLOWS 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_ANY_DSB_MISS EVENT_OPTION_MATCH0=0x1
#UMASK_FRONTEND_RETIRED_ANY_DSB_MISS 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_LATENCY_GE_1 EVENT_OPTION_MATCH0=0x600106
#UMASK_FRONTEND_RETIRED_LATENCY_GE_1 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_LATENCY_GE_2 EVENT_OPTION_MATCH0=0x600206
#UMASK_FRONTEND_RETIRED_LATENCY_GE_2 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_1 EVENT_OPTION_MATCH0=0x100206
#UMASK_FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_1 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_LATENCY_GE_4 EVENT_OPTION_MATCH0=0x600406
#UMASK_FRONTEND_RETIRED_LATENCY_GE_4 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_LATENCY_GE_16 EVENT_OPTION_MATCH0=0x601006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_8 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_LATENCY_GE_8 EVENT_OPTION_MATCH0=0x600806
#UMASK_FRONTEND_RETIRED_LATENCY_GE_16 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_LATENCY_GE_32 EVENT_OPTION_MATCH0=0x602006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_32 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_LATENCY_GE_64 EVENT_OPTION_MATCH0=0x604006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_64 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_LATENCY_GE_128 EVENT_OPTION_MATCH0=0x608006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_128 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_LATENCY_GE_256 EVENT_OPTION_MATCH0=0x610006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_256 0x01
#DEFAULT_OPTIONS_FRONTEND_RETIRED_LATENCY_GE_512 EVENT_OPTION_MATCH0=0x620006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_512 0x01
EVENT_FP_ARITH_INST_RETIRED 0xC7 PMC
#DESC_FP_ARITH_INST_RETIRED_SCALAR_DOUBLE "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events."
UMASK_FP_ARITH_INST_RETIRED_SCALAR_DOUBLE 0x01
#DESC_FP_ARITH_INST_RETIRED_SCALAR_SINGLE "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events."
UMASK_FP_ARITH_INST_RETIRED_SCALAR_SINGLE 0x02
#DESC_FP_ARITH_INST_RETIRED_128B_PACKED_DOUBLE "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events."
UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_DOUBLE 0x04
#DESC_FP_ARITH_INST_RETIRED_128B_PACKED_SINGLE "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events."
UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_SINGLE 0x08
#DESC_FP_ARITH_INST_RETIRED_256B_PACKED_DOUBLE "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events."
UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_DOUBLE 0x10
#DESC_FP_ARITH_INST_RETIRED_256B_PACKED_SINGLE "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events."
UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_SINGLE 0x20
#DESC_FP_ARITH_INST_RETIRED_512B_PACKED_DOUBLE "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events."
UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_DOUBLE 0x40
#DESC_FP_ARITH_INST_RETIRED_512B_PACKED_SINGLE "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events."
UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_SINGLE 0x80
EVENT_FP_ARITH_INST_RETIRED2 0xCF PMC
UMASK_FP_ARITH_INST_RETIRED2_SCALAR_HALF 0x01
UMASK_FP_ARITH_INST_RETIRED2_COMPLEX_SCALAR_HALF 0x02
#DESC_FP_ARITH_INST_RETIRED2_SCALAR "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex."
UMASK_FP_ARITH_INST_RETIRED2_SCALAR 0x03
UMASK_FP_ARITH_INST_RETIRED2_128B_PACKED_HALF 0x04
UMASK_FP_ARITH_INST_RETIRED2_256B_PACKED_HALF 0x08
UMASK_FP_ARITH_INST_RETIRED2_512B_PACKED_HALF 0x10
#DESC_FP_ARITH_INST_RETIRED2_VECTOR "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired."
UMASK_FP_ARITH_INST_RETIRED2_VECTOR 0x1C
EVENT_RTM_RETIRED 0xC9 PMC
UMASK_RTM_RETIRED_START 0x01
UMASK_RTM_RETIRED_COMMIT 0x02
UMASK_RTM_RETIRED_ABORTED 0x04
UMASK_RTM_RETIRED_ABORTED_MEM 0x08
UMASK_RTM_RETIRED_ABORTED_UNFRIENDLY 0x20
UMASK_RTM_RETIRED_ABORTED_MEMTYPE 0x40
UMASK_RTM_RETIRED_ABORTED_EVENTS 0x80
EVENT_MISC_RETIRED 0xCC PMC
UMASK_MISC_RETIRED_LBR_INSERTS 0x20
# Register 0x3F6 and partly "TakenAlone"
# MEM_TRANS_RETIRED 0xCD
EVENT_AMX_OPS_RETIRED 0xCE PMC
UMASK_AMX_OPS_RETIRED_INT8 0x01
UMASK_AMX_OPS_RETIRED_BF16 0x02
EVENT_MEM_INST_RETIRED 0xD0 PMC
UMASK_MEM_INST_RETIRED_STLB_MISS_LOADS 0x11
UMASK_MEM_INST_RETIRED_STLB_MISS_STORES 0x12
UMASK_MEM_INST_RETIRED_LOCK_LOADS 0x21
UMASK_MEM_INST_RETIRED_SPLIT_LOADS 0x41
UMASK_MEM_INST_RETIRED_SPLIT_STORES 0x42
UMASK_MEM_INST_RETIRED_ALL_LOADS 0x81
UMASK_MEM_INST_RETIRED_ALL_STORES 0x82
UMASK_MEM_INST_RETIRED_ALL 0x83
EVENT_MEM_LOAD_RETIRED 0xD1 PMC
UMASK_MEM_LOAD_RETIRED_L1_HIT 0x01
UMASK_MEM_LOAD_RETIRED_L2_HIT 0x02
UMASK_MEM_LOAD_RETIRED_L3_HIT 0x04
UMASK_MEM_LOAD_RETIRED_L1_MISS 0x08
UMASK_MEM_LOAD_RETIRED_L2_MISS 0x10
UMASK_MEM_LOAD_RETIRED_L3_MISS 0x20
UMASK_MEM_LOAD_RETIRED_FB_HIT 0x40
UMASK_MEM_LOAD_RETIRED_LOCAL_PMM 0x80
EVENT_MEM_LOAD_L3_HIT_RETIRED 0xD2 PMC
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_MISS 0x01
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_NO_FWD 0x02
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_FWD 0x04
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_NONE 0x08
EVENT_MEM_LOAD_L3_MISS_RETIRED 0xD3 PMC
UMASK_MEM_LOAD_L3_MISS_RETIRED_LOCAL_DRAM 0x01
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_DRAM 0x02
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_HITM 0x04
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_FWD 0x08
UMASK_MEM_LOAD_L3_MISS_RETIRED_REMOTE_PMM 0x10
EVENT_MEM_LOAD_MISC_RETIRED 0xD4 PMC
UMASK_MEM_LOAD_MISC_RETIRED_UC 0x04
EVENT_MISC2_RETIRED_LFENCE 0xE0 PMC
UMASK_MISC2_RETIRED_LFENCE 0x20
EVENT_MEM_UOP_RETIRED_ANY 0xE5 PMC
UMASK_MEM_UOP_RETIRED_ANY 0x03
EVENT_INT_VEC_RETIRED 0xE7 PMC
#DESC_INT_VEC_RETIRED_ADD_128 "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions."
UMASK_INT_VEC_RETIRED_ADD_128 0x03
#DESC_INT_VEC_RETIRED_ADD_256 "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions."
UMASK_INT_VEC_RETIRED_ADD_256 0x0C
UMASK_INT_VEC_RETIRED_VNNI_128 0x10
UMASK_INT_VEC_RETIRED_VNNI_256 0x20
UMASK_INT_VEC_RETIRED_SHUFFLES 0x40
UMASK_INT_VEC_RETIRED_MUL_256 0x80
UMASK_INT_VEC_RETIRED_128BIT 0x13
UMASK_INT_VEC_RETIRED_256BIT 0xAC
EVENT_CPU_CLK_UNHALTED 0xEC PMC
UMASK_CPU_CLK_UNHALTED_DISTRIBUTED 0x02
UMASK_CPU_CLK_UNHALTED_C01 0x10
UMASK_CPU_CLK_UNHALTED_C02 0x20
UMASK_CPU_CLK_UNHALTED_PAUSE 0x40
DEFAULT_OPTIONS_CPU_CLK_UNHALTED_PAUSE_INST EVENT_OPTION_EDGE=0x1,EVENT_OPTION_THRESHOLD=0x1
UMASK_CPU_CLK_UNHALTED_PAUSE_INST 0x40
UMASK_CPU_CLK_UNHALTED_C0_WAIT 0x70
EVENT_OFFCORE_RESPONSE_0 0x2A PMC
OPTIONS_OFFCORE_RESPONSE_0_OPTIONS EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_MATCH1_MASK
UMASK_OFFCORE_RESPONSE_0_OPTIONS 0x01 0xFF 0xFF
EVENT_OFFCORE_RESPONSE_1 0x2B PMC
OPTIONS_OFFCORE_RESPONSE_1_OPTIONS EVENT_OPTION_MATCH0_MASK|EVENT_OPTION_MATCH1_MASK
UMASK_OFFCORE_RESPONSE_1_OPTIONS 0x01 0xFF 0xFF
# Uncore events based on version 1.15 of sapphirerapids_uncore_experimental.json
#######################################################
# UBOX == UBOX #
#######################################################
EVENT_EVENT_MSG 0x42 UBOX
UMASK_EVENT_MSG_VLW_RCVD 0x01
UMASK_EVENT_MSG_MSI_RCVD 0x02
UMASK_EVENT_MSG_IPI_RCVD 0x04
UMASK_EVENT_MSG_DOORBELL_RCVD 0x08
UMASK_EVENT_MSG_INT_PRIO 0x10
EVENT_PHOLD_CYCLES_ASSERT_TO_ACK 0x45 UBOX
UMASK_PHOLD_CYCLES_ASSERT_TO_ACK 0x01
EVENT_RACU_REQUESTS 0x46 UBOX
UMASK_RACU_REQUESTS 0x00
EVENT_RACU_DRNG 0x4C UBOX0
UMASK_RACU_DRNG_RDRAND 0x01
UMASK_RACU_DRNG_RDSEED 0x02
UMASK_RACU_DRNG_PFTCH_BUF_EMPTY 0x04
EVENT_M2U_MISC1 0x4D UBOX0
UMASK_M2U_MISC1_RXC_CYCLES_NE_CBO_NCB 0x01
UMASK_M2U_MISC1_RXC_CYCLES_NE_CBO_NCS 0x02
UMASK_M2U_MISC1_RXC_CYCLES_NE_UPI_NCB 0x04
UMASK_M2U_MISC1_RXC_CYCLES_NE_UPI_NCS 0x08
UMASK_M2U_MISC1_TXC_CYCLES_CRD_OVF_CBO_NCB 0x10
UMASK_M2U_MISC1_TXC_CYCLES_CRD_OVF_CBO_NCS 0x20
UMASK_M2U_MISC1_TXC_CYCLES_CRD_OVF_UPI_NCB 0x40
UMASK_M2U_MISC1_TXC_CYCLES_CRD_OVF_UPI_NCS 0x80
EVENT_M2U_MISC2 0x4E UBOX0
UMASK_M2U_MISC2_RXC_CYCLES_FULL_BL 0x01
UMASK_M2U_MISC2_RXC_CYCLES_EMPTY_BL 0x02
UMASK_M2U_MISC2_TXC_CYCLES_CRD_OVF_VN0_NCB 0x04
UMASK_M2U_MISC2_TXC_CYCLES_CRD_OVF_VN0_NCS 0x08
UMASK_M2U_MISC2_TXC_CYCLES_EMPTY_BL 0x10
UMASK_M2U_MISC2_TXC_CYCLES_EMPTY_AK 0x20
UMASK_M2U_MISC2_TXC_CYCLES_EMPTY_AKC 0x40
UMASK_M2U_MISC2_TXC_CYCLES_FULL_BL 0x80
EVENT_M2U_MISC3 0x4F UBOX0
UMASK_M2U_MISC3_TXC_CYCLES_FULL_AK 0x01
UMASK_M2U_MISC3_TXC_CYCLES_FULL_AKC 0x02
#######################################################
# IRP == IRP #
#######################################################
EVENT_IRP_CLOCKTICKS 0x01 IRP
UMASK_IRP_CLOCKTICKS 0x00
EVENT_MISC0 0x1E IRP
UMASK_MISC0_2ND_ATOMIC_INSERT 0x10
UMASK_MISC0_2ND_RD_INSERT 0x04
UMASK_MISC0_2ND_WR_INSERT 0x08
UMASK_MISC0_FAST_REJ 0x02
UMASK_MISC0_FAST_REQ 0x01
UMASK_MISC0_FAST_XFER 0x20
UMASK_MISC0_PF_ACK_HINT 0x40
UMASK_MISC0_SLOWPATH_FWPF_NO_PRF 0x80
EVENT_MISC1 0x1F IRP
UMASK_MISC1_SLOW_I 0x01
UMASK_MISC1_SLOW_S 0x02
UMASK_MISC1_SLOW_E 0x04
UMASK_MISC1_SLOW_M 0x08
UMASK_MISC1_SEC_RCVD_INVLD 0x20
UMASK_MISC1_SEC_RCVD_VLD 0x40
EVENT_IRP_ALL 0x20 IRP
UMASK_IRP_ALL_OUTBOUND_INSERTS 0x02
UMASK_IRP_ALL_EVICTS 0x04
EVENT_TXC_AK_INSERTS 0x0B IRP
UMASK_TXC_AK_INSERTS 0x00
EVENT_TXC_BL_DRS_CYCLES_FULL 0x05 IRP
UMASK_TXC_BL_DRS_CYCLES_FULL 0x00
EVENT_TXC_BL_DRS_INSERTS 0x02 IRP
UMASK_TXC_BL_DRS_INSERTS 0x00
EVENT_TXC_BL_DRS_OCCUPANCY 0x08 IRP
UMASK_TXC_BL_DRS_OCCUPANCY 0x00
EVENT_TXC_BL_NCB_CYCLES_FULL 0x06 IRP
UMASK_TXC_BL_NCB_CYCLES_FULL 0x00
EVENT_TXC_BL_NCB_INSERTS 0x03 IRP
UMASK_TXC_BL_NCB_INSERTS 0x00
EVENT_TXC_BL_NCB_OCCUPANCY 0x09 IRP
UMASK_TXC_BL_NCB_OCCUPANCY 0x00
EVENT_TXC_BL_NCS_CYCLES_FULL 0x07 IRP
UMASK_TXC_BL_NCS_CYCLES_FULL 0x00
EVENT_TXC_BL_NCS_INSERTS 0x04 IRP
UMASK_TXC_BL_NCS_INSERTS 0x00
EVENT_TXC_BL_NCS_OCCUPANCY 0x0A IRP
UMASK_TXC_BL_NCS_OCCUPANCY 0x00
EVENT_TXR2_AD0_STALL_CREDIT_CYCLES 0x1A IRP
UMASK_TXR2_AD0_STALL_CREDIT_CYCLES 0x00
EVENT_TXR2_AD01_STALL_CREDIT_CYCLES 0x1C IRP
UMASK_TXR2_AD01_STALL_CREDIT_CYCLES 0x00
EVENT_TXR2_AD1_STALL_CREDIT_CYCLES 0x1B IRP
UMASK_TXR2_AD1_STALL_CREDIT_CYCLES 0x00
EVENT_TXR2_BL_STALL_CREDIT_CYCLES 0x1D IRP
UMASK_TXR2_BL_STALL_CREDIT_CYCLES 0x00
EVENT_TXS_DATA_INSERTS_NCB 0x0D IRP
UMASK_TXS_DATA_INSERTS_NCB 0x00
EVENT_TXS_DATA_INSERTS_NCS 0x0E IRP
UMASK_TXS_DATA_INSERTS_NCS 0x00
EVENT_TXS_REQUEST_OCCUPANCY 0x0C IRP
UMASK_TXS_REQUEST_OCCUPANCY 0x00
EVENT_CACHE_TOTAL_OCCUPANCY 0x0F IRP
UMASK_CACHE_TOTAL_OCCUPANCY_MEM 0x04
EVENT_SNOOP_RESP 0x12 IRP
UMASK_SNOOP_RESP_ALL_HIT 0x7E
UMASK_SNOOP_RESP_ALL_HIT_ES 0x74
UMASK_SNOOP_RESP_ALL_HIT_I 0x72
UMASK_SNOOP_RESP_ALL_MISS 0x71
UMASK_SNOOP_RESP_HIT_ES 0x04
UMASK_SNOOP_RESP_HIT_I 0x02
UMASK_SNOOP_RESP_HIT_M 0x08
UMASK_SNOOP_RESP_MISS 0x01
UMASK_SNOOP_RESP_SNPCODE 0x10
UMASK_SNOOP_RESP_SNPDATA 0x20
UMASK_SNOOP_RESP_SNPINV 0x40
#######################################################
# IIO == IIO #
#######################################################
EVENT_IIO_CLOCKTICKS 0x01 IIO
UMASK_IIO_CLOCKTICKS 0x00
EVENT_MASK_MATCH_AND 0x02 IIO
UMASK_MASK_MATCH_AND_BUS0 0x01
UMASK_MASK_MATCH_AND_BUS1 0x02
UMASK_MASK_MATCH_AND_BUS0_NOT_BUS1 0x04
UMASK_MASK_MATCH_AND_BUS0_BUS1 0x08
UMASK_MASK_MATCH_AND_NOT_BUS0_BUS1 0x10
UMASK_MASK_MATCH_AND_NOT_BUS0_NOT_BUS1 0x20
EVENT_MASK_MATCH_OR 0x03 IIO
UMASK_MASK_MATCH_OR_BUS0 0x01
UMASK_MASK_MATCH_OR_BUS1 0x02
UMASK_MASK_MATCH_OR_BUS0_NOT_BUS1 0x04
UMASK_MASK_MATCH_OR_BUS0_BUS1 0x08
UMASK_MASK_MATCH_OR_NOT_BUS0_BUS1 0x10
UMASK_MASK_MATCH_OR_NOT_BUS0_NOT_BUS1 0x20
EVENT_IIO_IOMMU0 0x40 IIO0C0|IIO1C0|IIO2C0|IIO3C0|IIO4C0|IIO5C0|IIO6C0|IIO7C0|IIO8C0|IIO9C0|IIO10C0|IIO11C0|IIO12C0|IIO13C0|IIO14C0|IIO15C0
UMASK_IIO_IOMMU0_MISSES 0x20
EVENT_IIO_PWT_OCCUPANCY 0x42 IIO
UMASK_IIO_PWT_OCCUPANCY 0xFF
EVENT_PWT_OCCUPANCY 0x42 IIO
UMASK_PWT_OCCUPANCY 0xFF
EVENT_COMP_BUF_INSERTS 0xC2 IIO
UMASK_COMP_BUF_INSERTS_CMPD_ALL_PARTS 0x04
EVENT_COMP_BUF_OCCUPANCY 0xD5 IIO
UMASK_COMP_BUF_OCCUPANCY_CMPD_ALL_PARTS 0xFF
EVENT_IOMMU1 0x41 IIO
UMASK_IOMMU1_SLPWC_1G_HITS 0x04
UMASK_IOMMU1_SLPWC_256T_HITS 0x10
UMASK_IOMMU1_SLPWC_512G_HITS 0x08
UMASK_IOMMU1_PWT_CACHE_LOOKUPS 0x01
UMASK_IOMMU1_PWC_2M_HITS 0x02
UMASK_IOMMU1_PWC_1G_HITS 0x04
UMASK_IOMMU1_PWC_512G_HITS 0x08
UMASK_IOMMU1_PWC_256T_HITS 0x10
UMASK_IOMMU1_PWC_CACHE_FILLS 0x20
EVENT_IOMMU3 0x43 IIO
UMASK_IOMMU3_PWT_OCCUPANCY_MSB 0x01
EVENT_IIO_DATA_REQ_OF_CPU 0x83 IIO
OPTIONS_IIO_DATA_REQ_OF_CPU EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART0 EVENT_OPTION_MATCH0=0x00070010
UMASK_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART0 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART1 EVENT_OPTION_MATCH0=0x00070020
UMASK_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART1 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART2 EVENT_OPTION_MATCH0=0x00070040
UMASK_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART2 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART3 EVENT_OPTION_MATCH0=0x00070080
UMASK_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART3 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART4 EVENT_OPTION_MATCH0=0x00070100
UMASK_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART4 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART5 EVENT_OPTION_MATCH0=0x00070200
UMASK_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART5 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART6 EVENT_OPTION_MATCH0=0x00070400
UMASK_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART6 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART7 EVENT_OPTION_MATCH0=0x00070800
UMASK_IIO_DATA_REQ_OF_CPU_PEER_WRITE_PART7 0x02
EVENT_IIO_DATA_REQ_BY_CPU 0xC2 IIO
OPTIONS_IIO_DATA_REQ_BY_CPU EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART0 EVENT_OPTION_MATCH0=0x00070010
UMASK_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART0 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART1 EVENT_OPTION_MATCH0=0x00070020
UMASK_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART1 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART2 EVENT_OPTION_MATCH0=0x00070040
UMASK_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART2 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART3 EVENT_OPTION_MATCH0=0x00070080
UMASK_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART3 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART4 EVENT_OPTION_MATCH0=0x00070100
UMASK_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART4 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART5 EVENT_OPTION_MATCH0=0x00070200
UMASK_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART5 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART6 EVENT_OPTION_MATCH0=0x00070400
UMASK_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART6 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART7 EVENT_OPTION_MATCH0=0x00070800
UMASK_IIO_DATA_REQ_BY_CPU_PEER_WRITE_PART7 0x02
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_READ_PART0 EVENT_OPTION_MATCH0=0x00070010
UMASK_IIO_DATA_REQ_BY_CPU_PEER_READ_PART0 0x08
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_READ_PART1 EVENT_OPTION_MATCH0=0x00070020
UMASK_IIO_DATA_REQ_BY_CPU_PEER_READ_PART1 0x08
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_READ_PART2 EVENT_OPTION_MATCH0=0x00070040
UMASK_IIO_DATA_REQ_BY_CPU_PEER_READ_PART2 0x08
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_READ_PART3 EVENT_OPTION_MATCH0=0x00070080
UMASK_IIO_DATA_REQ_BY_CPU_PEER_READ_PART3 0x08
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_READ_PART4 EVENT_OPTION_MATCH0=0x00070100
UMASK_IIO_DATA_REQ_BY_CPU_PEER_READ_PART4 0x08
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_READ_PART5 EVENT_OPTION_MATCH0=0x00070200
UMASK_IIO_DATA_REQ_BY_CPU_PEER_READ_PART5 0x08
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_READ_PART6 EVENT_OPTION_MATCH0=0x00070400
UMASK_IIO_DATA_REQ_BY_CPU_PEER_READ_PART6 0x08
DEFAULT_OPTIONS_IIO_DATA_REQ_BY_CPU_PEER_READ_PART7 EVENT_OPTION_MATCH0=0x00070800
UMASK_IIO_DATA_REQ_BY_CPU_PEER_READ_PART7 0x08
#EVENT_DATA_REQ_OF_CPU 0x83 IIO
#UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART0 0x02
#UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART1 0x02
#UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART2 0x02
#UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART3 0x02
#UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART4 0x02
#UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART5 0x02
#UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART6 0x02
#UMASK_DATA_REQ_OF_CPU_PEER_WRITE_PART7 0x02
EVENT_INBOUND_ARB_REQ 0x86 IIO
OPTIONS_INBOUND_ARB_REQ EVENT_OPTION_MATCH0_MASK
UMASK_INBOUND_ARB_REQ_IOMMU_REQ 0x01
UMASK_INBOUND_ARB_REQ_IOMMU_HIT 0x02
DEFAULT_OPTIONS_INBOUND_ARB_REQ_REQ_OWN EVENT_OPTION_MATCH0=0x00070FF0
UMASK_INBOUND_ARB_REQ_REQ_OWN 0x04
UMASK_INBOUND_ARB_REQ_FINAL_RD_WR 0x08
DEFAULT_OPTIONS_INBOUND_ARB_REQ_WR EVENT_OPTION_MATCH0=0x00070FF0
UMASK_INBOUND_ARB_REQ_WR 0x10
DEFAULT_OPTIONS_INBOUND_ARB_REQ_DATA EVENT_OPTION_MATCH0=0x00070FF0
UMASK_INBOUND_ARB_REQ_DATA 0x20
EVENT_INBOUND_ARB_WON 0x87 IIO
OPTIONS_INBOUND_ARB_WON EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_INBOUND_ARB_WON_IOMMU_REQ EVENT_OPTION_MATCH0=0x00070FF0
UMASK_INBOUND_ARB_WON_IOMMU_REQ 0x01
DEFAULT_OPTIONS_INBOUND_ARB_WON_IOMMU_HIT EVENT_OPTION_MATCH0=0x00070FF0
UMASK_INBOUND_ARB_WON_IOMMU_HIT 0x02
DEFAULT_OPTIONS_INBOUND_ARB_WON_REQ_OWN EVENT_OPTION_MATCH0=0x00070FF0
UMASK_INBOUND_ARB_WON_REQ_OWN 0x04
DEFAULT_OPTIONS_INBOUND_ARB_WON_FINAL_RD_WR EVENT_OPTION_MATCH0=0x00070FF0
UMASK_INBOUND_ARB_WON_FINAL_RD_WR 0x08
DEFAULT_OPTIONS_INBOUND_ARB_WON_WR EVENT_OPTION_MATCH0=0x00070FF0
UMASK_INBOUND_ARB_WON_WR 0x10
DEFAULT_OPTIONS_INBOUND_ARB_WON_DATA EVENT_OPTION_MATCH0=0x00070FF0
UMASK_INBOUND_ARB_WON_DATA 0x20
EVENT_NUM_REQ_OF_CPU_BY_TGT 0x8E IIO
UMASK_NUM_REQ_OF_CPU_BY_TGT_MSGB 0x01
UMASK_NUM_REQ_OF_CPU_BY_TGT_MCAST 0x02
UMASK_NUM_REQ_OF_CPU_BY_TGT_UBOX 0x04
UMASK_NUM_REQ_OF_CPU_BY_TGT_MEM 0x08
UMASK_NUM_REQ_OF_CPU_BY_TGT_REM_P2P 0x10
UMASK_NUM_REQ_OF_CPU_BY_TGT_LOC_P2P 0x20
UMASK_NUM_REQ_OF_CPU_BY_TGT_CONFINED_P2P 0x40
UMASK_NUM_REQ_OF_CPU_BY_TGT_ABORT 0x80
EVENT_REQ_FROM_PCIE_PASS_CMPL 0x90 IIO
OPTIONS_REQ_FROM_PCIE_PASS_CMPL EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_REQ_FROM_PCIE_PASS_CMPL_REQ_OWN EVENT_OPTION_MATCH0=0x00070FF0
UMASK_REQ_FROM_PCIE_PASS_CMPL_REQ_OWN 0x04
UMASK_REQ_FROM_PCIE_PASS_CMPL_FINAL_RD_WR 0x08
DEFAULT_OPTIONS_REQ_FROM_PCIE_PASS_CMPL_WR EVENT_OPTION_MATCH0=0x00070FF0
UMASK_REQ_FROM_PCIE_PASS_CMPL_WR 0x10
DEFAULT_OPTIONS_REQ_FROM_PCIE_PASS_CMPL_DATA EVENT_OPTION_MATCH0=0x00070FF0
UMASK_REQ_FROM_PCIE_PASS_CMPL_DATA 0x20
EVENT_REQ_FROM_PCIE_CL_CMPL 0x91 IIO
OPTIONS_REQ_FROM_PCIE_CL_CMPL EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_REQ_FROM_PCIE_CL_CMPL_REQ_OWN EVENT_OPTION_MATCH0=0x00070FF0
UMASK_REQ_FROM_PCIE_CL_CMPL_REQ_OWN 0x04
DEFAULT_OPTIONS_REQ_FROM_PCIE_CL_CMPL_FINAL_RD_WR EVENT_OPTION_MATCH0=0x00070FF0
UMASK_REQ_FROM_PCIE_CL_CMPL_FINAL_RD_WR 0x08
DEFAULT_OPTIONS_REQ_FROM_PCIE_CL_CMPL_WR EVENT_OPTION_MATCH0=0x00070FF0
UMASK_REQ_FROM_PCIE_CL_CMPL_WR 0x10
DEFAULT_OPTIONS_REQ_FROM_PCIE_CL_CMPL_DATA EVENT_OPTION_MATCH0=0x00070FF0
UMASK_REQ_FROM_PCIE_CL_CMPL_DATA 0x20
EVENT_REQ_FROM_PCIE_CMPL 0x92 IIO
OPTIONS_REQ_FROM_PCIE_CMPL EVENT_OPTION_MATCH0_MASK
DEFAULT_OPTIONS_REQ_FROM_PCIE_CMPL_IOMMU_REQ EVENT_OPTION_MATCH0=0x00070FF0
UMASK_REQ_FROM_PCIE_CMPL_IOMMU_REQ 0x01
DEFAULT_OPTIONS_REQ_FROM_PCIE_CMPL_IOMMU_HIT EVENT_OPTION_MATCH0=0x00070FF0
UMASK_REQ_FROM_PCIE_CMPL_IOMMU_HIT 0x02
DEFAULT_OPTIONS_REQ_FROM_PCIE_CMPL_REQ_OWN EVENT_OPTION_MATCH0=0x00070FF0
UMASK_REQ_FROM_PCIE_CMPL_REQ_OWN 0x04
DEFAULT_OPTIONS_REQ_FROM_PCIE_CMPL_FINAL_RD_WR EVENT_OPTION_MATCH0=0x00070FF0
UMASK_REQ_FROM_PCIE_CMPL_FINAL_RD_WR 0x08
EVENT_OUTBOUND_CL_REQS_ISSUED 0xD0 IIO
UMASK_OUTBOUND_CL_REQS_ISSUED_TO_IO 0x08
EVENT_OUTBOUND_TLP_REQS_ISSUED 0xD1 IIO
UMASK_OUTBOUND_TLP_REQS_ISSUED_TO_IO 0x08
#######################################################
# CBOX == CHA #
#######################################################
EVENT_CBOX_CLOCKTICKS 0x01 CBOX
UMASK_CBOX_CLOCKTICKS 0x00
EVENT_CHA_REQUESTS 0x50 CBOX
UMASK_CHA_REQUESTS_READS_LOCAL 0x01
UMASK_CHA_REQUESTS_READS_REMOTE 0x02
UMASK_CHA_REQUESTS_READS 0x03
UMASK_CHA_REQUESTS_WRITES_LOCAL 0x04
UMASK_CHA_REQUESTS_WRITES_REMOTE 0x08
UMASK_CHA_REQUESTS_WRITES 0x0C
UMASK_CHA_REQUESTS_INVITOE 0x30
EVENT_SNOOPS_SENT 0x51 CBOX
UMASK_SNOOPS_SENT_ALL 0x01
UMASK_SNOOPS_SENT_LOCAL 0x04
UMASK_SNOOPS_SENT_REMOTE 0x08
UMASK_SNOOPS_SENT_BCST_LOCAL 0x10
UMASK_SNOOPS_SENT_BCST_REMOTE 0x20
UMASK_SNOOPS_SENT_DIRECT_LOCAL 0x40
UMASK_SNOOPS_SENT_DIRECT_REMOTE 0x80
EVENT_DIR_LOOKUP 0x53 CBOX
UMASK_DIR_LOOKUP_NO_SNP 0x02
UMASK_DIR_LOOKUP_SNP 0x01
EVENT_DIR_UPDATE 0x54 CBOX
UMASK_DIR_UPDATE_HA 0x01
UMASK_DIR_UPDATE_TOR 0x02
EVENT_OSB 0x55 CBOX
UMASK_OSB_LOCAL_INVITOE 0x01
UMASK_OSB_LOCAL_READ 0x02
UMASK_OSB_REMOTE_READ 0x04
UMASK_OSB_REMOTE_READINVITOE 0x08
UMASK_OSB_RFO_HITS_SNP_BCAST 0x10
UMASK_OSB_OFF_PWRHEURISTIC 0x20
EVENT_WB_PUSH_MTOI 0x56 CBOX
UMASK_WB_PUSH_MTOI_LLC 0x01
UMASK_WB_PUSH_MTOI_MEM 0x02
EVENT_BYPASS_CHA_IMC 0x57 CBOX
UMASK_BYPASS_CHA_IMC_TAKEN 0x01
UMASK_BYPASS_CHA_IMC_INTERMEDIATE 0x02
UMASK_BYPASS_CHA_IMC_NOT_TAKEN 0x04
EVENT_READ_NO_CREDITS 0x58 CBOX
UMASK_READ_NO_CREDITS_MC0 0x01
UMASK_READ_NO_CREDITS_MC1 0x02
UMASK_READ_NO_CREDITS_MC2 0x04
UMASK_READ_NO_CREDITS_MC3 0x08
UMASK_READ_NO_CREDITS_MC4 0x10
UMASK_READ_NO_CREDITS_MC5 0x20
EVENT_IMC_READS_COUNT 0x59 CBOX
UMASK_IMC_READS_COUNT_PRIORITY 0x02
EVENT_WRITE_NO_CREDITS 0x5A CBOX
UMASK_WRITE_NO_CREDITS_MC0 0x01
UMASK_WRITE_NO_CREDITS_MC1 0x02
UMASK_WRITE_NO_CREDITS_MC2 0x04
UMASK_WRITE_NO_CREDITS_MC3 0x08
UMASK_WRITE_NO_CREDITS_MC4 0x10
UMASK_WRITE_NO_CREDITS_MC5 0x20
EVENT_IMC_WRITES_COUNT 0x5B CBOX
UMASK_IMC_WRITES_COUNT_PARTIAL 0x02
UMASK_IMC_WRITES_COUNT_FULL_PRIORITY 0x04
UMASK_IMC_WRITES_COUNT_PARTIAL_PRIORITY 0x08