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device_driver_and_transmitter.smv
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MODULE GLOBAL
DEFINE
HW_MEMORY_START := 0b2_01;
HW_MEMORY_END := 0b2_11;
RAM_START := 0b2_01;
RAM_END := 0b2_10;
VAR
RESET: word[1];
HDP: word[2];
TEARDOWN: word[1];
open_state: {
open_idle,
open_set_reset,
open_reset_test
};
turn: {
software,
HW_tx,
HW_td,
HW_init
};
HW_MEMORY_NDP: array 0..3 of word[2];
HW_MEMORY_BP: array 0..3 of word[2];
HW_MEMORY_BL: array 0..3 of word[2];
HW_MEMORY_OWN: array 0..3 of word[1];
HW_MEMORY_EOQ: array 0..3 of word[1];
pa: word[2];
length: word[2];
queue_head: word[2];
queue_tail: word[2];
new_bd: word[2];
MODULE device_driver(g)
VAR
-- TODO move open_state here?
transmit_state: {
transmit_idle,
transmit_update_queue,
transmit_bad_buffer_or_queue_full_or_not_queue_full,
transmit_updated_new_bd,
transmit_check_mis_queue
};
stop_state: {
stop_idle,
stop_set_teardown,
stop_teardown_test
};
last_run_function: {
none,
open,
transmit,
stop
};
open_has_run: boolean;
DEFINE
TRANSMIT_OVERFLOW :=
g.pa + g.length < g.pa;
TRANSMIT_LENGTH_EQ_ZERO :=
g.length = 0d2_0;
TRANSMIT_INSIDE_RAM :=
g.RAM_START <= g.pa &
g.pa + g.length - 0b2_01 <= g.RAM_END;
TRANSMIT_QUEUE_FULL :=
(
g.queue_head < g.queue_tail &
g.queue_head = g.HW_MEMORY_START &
g.queue_tail = g.HW_MEMORY_END
) | (
g.queue_tail < g.queue_head &
g.queue_tail + 0b2_01 = g.queue_head
);
TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL :=
TRANSMIT_OVERFLOW |
TRANSMIT_LENGTH_EQ_ZERO | !
TRANSMIT_INSIDE_RAM |
TRANSMIT_QUEUE_FULL;
ASSIGN
-- TODO is open_state initualized anywhere?
-- TODO is dead initualized anywhere?
init(transmit_state) := transmit_idle;
init(stop_state) := stop_idle;
-- TODO what does this comment mean?
-- The open state is g.turned on at power on
init(open_has_run) := FALSE;
init(last_run_function) := none;
next(open_has_run) := case
g.open_state = open_reset_test &
next(g.open_state) = open_idle
:
TRUE;
TRUE
:
open_has_run;
esac;
next(last_run_function) := case
g.open_state != open_idle &
next(g.open_state) = open_idle
:
open;
transmit_state != transmit_idle &
next(transmit_state) = transmit_idle
:
transmit;
stop_state != stop_idle &
next(stop_state) = stop_idle
:
stop;
TRUE
:
last_run_function;
esac;
next(g.open_state) := case
-- TODO do we want to stop open from runninng while another active? Seems like a good place...
g.open_state = open_idle &
--transmit_state = transmit_idle & next(transmit_state) = transmit_idle &
--stop_state = stop_idle & next(stop_state) = stop_idle &
g.turn = software
:
{open_set_reset, open_idle};
g.open_state = open_set_reset &
g.turn = software
:
open_reset_test;
g.open_state = open_reset_test &
g.RESET != 0b1_1 &
g.turn = software
:
open_idle;
TRUE
:
g.open_state;
esac;
next(transmit_state) := case
g.open_state = open_idle &
next(g.open_state) = open_idle &
transmit_state = transmit_idle &
-- TODO But this allows for executing both stop and transmit at the same time right?
-- CHANGE: cant have it recursively defined
--stop_state = stop_idle &
--next(stop_state) = stop_idle &
g.turn = software
:
{transmit_update_queue, transmit_idle};
transmit_state = transmit_update_queue &
!(
g.queue_head != 0b2_00 &
g.HW_MEMORY_OWN[g.queue_head] = 0b1_0
) &
g.turn = software
:
transmit_bad_buffer_or_queue_full_or_not_queue_full;
-- TODO Added this from pseudocode, not in original transitions. Tell daniel.
transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full &
TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL &
g.turn = software
:
transmit_idle;
transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full &
!TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL &
g.HDP = 0b2_00 &
g.turn = software
:
transmit_idle;
transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full &
!TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL &
g.HDP != 0b2_00 &
g.turn = software
:
transmit_updated_new_bd;
transmit_state = transmit_updated_new_bd &
g.turn = software
:
transmit_check_mis_queue;
transmit_state = transmit_check_mis_queue &
g.turn = software
:
transmit_idle;
TRUE
:
transmit_state;
esac;
next(stop_state) := case
-- TODO whats the policy on starting funcitons?
g.open_state = open_idle &
next(g.open_state) = open_idle &
transmit_state = transmit_idle &
next(transmit_state) = transmit_idle &
stop_state = stop_idle &
g.turn = software
:
{stop_idle, stop_set_teardown};
stop_state = stop_set_teardown &
g.turn = software
:
stop_teardown_test;
stop_state = stop_teardown_test &
-- This next line was missing from pseudocode new var info
g.TEARDOWN = 0b1_0 &
g.turn = software
:
stop_idle;
TRUE
:
stop_state;
esac;
INVAR -- only one function can run at a time
(g.open_state != open_idle & transmit_state = transmit_idle & stop_state = stop_idle ) |
(g.open_state = open_idle & transmit_state != transmit_idle & stop_state = stop_idle ) |
(g.open_state = open_idle & transmit_state = transmit_idle & stop_state != stop_idle ) |
(g.open_state = open_idle & transmit_state = transmit_idle & stop_state = stop_idle );
INVAR -- open runs first
open_has_run | (transmit_state = transmit_idle & stop_state = stop_idle);
INVAR -- open cant run after transmit
(last_run_function != transmit) | (g.open_state = open_idle);
MODULE transmitter(g)
VAR
it_state: {
it_idle,
it_resetting,
it_waiting_hdp
};
tx_state: {
tx_idle,
tx_fetching_bd,
tx_reading_memory,
tx_setting_eoq_or_releasing_bd,
tx_releasing_bd
};
td_state: {
td_idle,
td_waiting_for_tx,
td_releasing_bd,
td_clearing_td
};
dead: boolean;
last_run_function: {none, it, tx, td};
it_has_run: boolean;
DEFINE
TX_BUFFER_OVERFLOW :=
g.HW_MEMORY_BP[g.HDP] + g.HW_MEMORY_BL[g.HDP] < g.HW_MEMORY_BP[g.HDP];
TX_BUFFER_INSIDE_RAM :=
g.RAM_START <= g.HW_MEMORY_BP[g.HDP] &
g.HW_MEMORY_BP[g.HDP] + g.HW_MEMORY_BL[g.HDP] - 0b2_01 <= g.RAM_END;
HW_MEMORY_START := 0b2_01;
HW_MEMORY_END := 0b2_11;
RAM_START := 0b2_01;
RAM_END := 0b2_10;
ASSIGN
init(it_state) := it_idle;
init(tx_state) := tx_idle;
init(td_state) := td_idle;
init(dead) := FALSE;
init(last_run_function) := none;
init(it_has_run) := FALSE;
next(it_has_run) := case
it_state != it_idle &
next(it_state) = it_idle
:
TRUE;
TRUE : it_has_run;
esac;
next(last_run_function) := case
it_state != it_idle &
next(it_state) = it_idle
:
it;
tx_state != tx_idle &
next(tx_state) = tx_idle
:
tx;
td_state != td_idle &
next(td_state) = td_idle
:
td;
TRUE: last_run_function;
esac;
next(it_state) := case
it_state = it_idle &
g.RESET = 0b1_0 &
next(g.RESET) = 0b1_1 &
-- TODO personal opinion, the following two dont seem necessary. //J
g.open_state = open_set_reset &
next(g.open_state) = open_reset_test &
g.turn = software
:
it_resetting;
it_state = it_resetting &
g.turn = HW_init
:
it_waiting_hdp;
it_state = it_waiting_hdp &
next(g.HDP) = 0b2_0 &
g.open_state = open_reset_test &
next(g.open_state) = open_idle &
g.turn = software
:
it_idle;
TRUE : it_state;
esac;
next(dead) := case
-- TODO this should replace many invars right?
tx_state = tx_fetching_bd &
(
g.HW_MEMORY_OWN[g.HDP] = 0b1_0 |
g.HW_MEMORY_EOQ[g.HDP] = 0b1_1 |
g.HW_MEMORY_BL[g.HDP] = 0b2_00 |
TX_BUFFER_OVERFLOW |
!TX_BUFFER_INSIDE_RAM
) &
g.turn = HW_tx
:
TRUE;
TRUE : dead;
esac;
next(tx_state) := case
tx_state = tx_idle &
g.HDP = 0b2_00 &
next(g.HDP) != 0b2_00 &
g.turn = software
:
tx_fetching_bd;
-- TODO Does this dead-update happen?
tx_state = tx_fetching_bd &
!(
g.HW_MEMORY_OWN[g.HDP] = 0b1_0 |
g.HW_MEMORY_EOQ[g.HDP] = 0b1_1 |
g.HW_MEMORY_BL[g.HDP] = 0b2_0 |
TX_BUFFER_OVERFLOW |
!TX_BUFFER_INSIDE_RAM
) &
g.turn = HW_tx
:
tx_reading_memory;
tx_state = tx_reading_memory &
g.turn = HW_tx
:
tx_setting_eoq_or_releasing_bd;
tx_state = tx_setting_eoq_or_releasing_bd &
g.turn = HW_tx
:
case
g.HW_MEMORY_NDP[g.HDP] = 0b2_00 : tx_releasing_bd;
td_state = td_waiting_for_tx : tx_idle;
TRUE : tx_fetching_bd;
esac;
tx_state = tx_releasing_bd &
g.turn = HW_tx
: tx_idle;
TRUE: tx_state;
esac;
next(td_state) := case
td_state = td_idle &
g.TEARDOWN = 0b1_0 &
next(g.TEARDOWN) = 0b1_1 &
g.turn = software
:
td_waiting_for_tx;
td_state = td_waiting_for_tx &
tx_state = tx_idle &
g.HDP = 0b2_00 &
g.turn = HW_td
:
td_idle;
td_state = td_waiting_for_tx &
tx_state = tx_idle &
g.HDP != 0b2_00 &
g.turn = HW_td
:
td_releasing_bd;
td_state = td_releasing_bd &
g.turn = HW_td
:
td_clearing_td;
td_state = td_clearing_td &
g.turn = HW_td
:
td_idle;
TRUE: td_state;
esac;
--INVAR
-- Initialization works as follows. Write 1 to g.RESET. The transmitter then
-- resets itself. When the transmitter has finished the resetting, g.RESET is
-- set to 0. Then the software writes zero to g.HDP. This sequence of steps
-- initializes the transmitter. Any other sequence operations during
-- initialization is erronous.
-- (it_state = it_idle | (tx_state = tx_idle & td_state = td_idle)) &
-- -- If the transmitter performs a reset, then open is currently executed
-- (g.RESET = 0d1_0 | g.open_state != open_idle) &
-- If the transmitter performs a tear down, then the transmitter is not
--performing a reset.
-- (g.TEARDOWN = 0d1_0 | g.RESET = 0d1_0) &
-- (g.RESET = 0d1_0 | (g.TEARDOWN = 0d1_0 & tx_state = tx_idle)) &
-- CHANGE: require init runs first
-- ((tx_state = tx_idle & td_state = td_idle) | it_has_run);
MODULE main
VAR
g: GLOBAL;
t_smit: transmitter(g);
d_rive: device_driver(g);
ASSIGN
init(g.RESET) := 0b1_0;
init(g.TEARDOWN) := 0b1_0;
init(g.open_state) := open_idle;
--init(g.turn) := software;
init(g.pa) := 0d2_2;
init(g.length) := 0d2_1;
init(g.queue_tail) := 0d2_03;
init(g.queue_head) := 0d2_03;
init(g.HW_MEMORY_OWN[0]) := 0d1_00;
init(g.HW_MEMORY_OWN[1]) := 0d1_01;
init(g.HW_MEMORY_OWN[2]) := 0d1_00;
init(g.HW_MEMORY_OWN[3]) := 0d1_00;
init(g.HW_MEMORY_NDP[0]) := 0d2_00;
init(g.HW_MEMORY_NDP[1]) := 0d2_00;
init(g.HW_MEMORY_NDP[2]) := 0d2_00;
init(g.HW_MEMORY_NDP[3]) := 0d2_00;
init(g.HW_MEMORY_BP[0]) := 0d2_01;
init(g.HW_MEMORY_BP[1]) := 0d2_00;
init(g.HW_MEMORY_BP[2]) := 0d2_00;
init(g.HW_MEMORY_BP[3]) := 0d2_00;
init(g.HW_MEMORY_BL[0]) := 0d2_00;
init(g.HW_MEMORY_BL[1]) := 0d2_00;
init(g.HW_MEMORY_BL[2]) := 0d2_00;
init(g.HW_MEMORY_BL[3]) := 0d2_00;
init(g.HW_MEMORY_EOQ[0]) := 0d1_00;
init(g.HW_MEMORY_EOQ[1]) := 0d1_00;
init(g.HW_MEMORY_EOQ[2]) := 0d1_00;
init(g.HW_MEMORY_EOQ[3]) := 0d1_00;
next(g.RESET) := case
g.open_state = open_set_reset &
next(g.open_state) = open_reset_test &
g.turn = software
:
0b1_1;
t_smit.it_state = it_resetting &
g.turn = HW_init
:
0b1_0;
TRUE: g.RESET;
esac;
-- TODO So uh were just doing nondet trnasitions?
--next(g.turn) :=
-- case
-- next(t_smit.td_state) != td_idle: HW_td;
-- next(t_smit.tx_state) != tx_idle: HW_tx;
-- next(t_smit.it_state) != it_idle: HW_init;
-- next(d_rive.g.open_state) != open_idle | d_rive.transmit_state != transmit_idle | d_rive.stop_state != stop_idle: software;
-- TRUE: g.turn;
-- esac;
next(g.turn) := {HW_td, HW_tx, HW_init, software};
next(g.new_bd) := case
d_rive.transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full &
!d_rive.TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL &
g.HDP != 0b2_00 &
g.turn = software
:
case
g.queue_tail = g.HW_MEMORY_END : g.HW_MEMORY_START;
TRUE : g.queue_tail + 0b2_01;
esac;
-- TODO addition LJ
TRUE: g.new_bd;
esac;
next(g.HDP) := case
g.open_state = open_reset_test &
next(g.open_state) = open_idle &
g.turn = software
:
0b2_00;
d_rive.transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full &
!d_rive.TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL &
g.HDP = 0b2_00 &
g.turn = software
:
g.HW_MEMORY_START;
d_rive.transmit_state = transmit_check_mis_queue &
g.HW_MEMORY_OWN[g.queue_tail] = 0b1_0 &
g.HW_MEMORY_EOQ[g.queue_tail] = 0b1_1 &
g.HW_MEMORY_NDP[g.queue_tail] != 0b2_00 &
g.turn = software
:
g.new_bd;
t_smit.tx_state = tx_setting_eoq_or_releasing_bd &
g.HW_MEMORY_NDP[g.HDP] != 0b2_00 &
g.turn = HW_tx
:
g.HW_MEMORY_NDP[g.HDP];
t_smit.tx_state = tx_releasing_bd &
g.turn = HW_tx
:
0b2_00;
t_smit.td_state = td_releasing_bd &
g.turn = HW_td
:
0b2_00;
TRUE: g.HDP;
esac;
next(g.TEARDOWN) := case
d_rive.stop_state = stop_set_teardown &
next(d_rive.stop_state) = stop_teardown_test &
g.turn = software
:
0b1_1;
t_smit.td_state = td_waiting_for_tx &
t_smit.tx_state = tx_idle &
g.HDP = 0b2_00 &
g.turn = HW_td
:
0b1_0;
t_smit.td_state = td_clearing_td &
g.turn = HW_td
:
0b1_0;
TRUE: g.TEARDOWN;
esac;
next(g.queue_head) := case
g.open_state = open_reset_test &
next(g.open_state) = open_idle &
g.turn = software
:
0b2_00;
d_rive.transmit_state = transmit_update_queue &
g.queue_head != 0d2_0 &
g.HW_MEMORY_OWN[g.queue_head] = 0b1_0 &
g.turn = software
:
g.HW_MEMORY_NDP[g.queue_head];
d_rive.transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full &
!d_rive.TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL &
g.HDP = 0b2_00 &
g.turn = software
:
g.HW_MEMORY_START;
d_rive.transmit_state = transmit_check_mis_queue &
g.HW_MEMORY_OWN[g.queue_tail] = 0b1_0 &
g.HW_MEMORY_EOQ[g.queue_tail] = 0b1_1 &
g.HW_MEMORY_NDP[g.queue_tail] != 0b2_00 &
g.turn = software
: g.new_bd;
d_rive.stop_state = stop_teardown_test &
next(d_rive.stop_state) = stop_idle &
g.turn = software
:
0b2_00;
TRUE: g.queue_head;
esac;
next(g.queue_tail) := case
d_rive.g.open_state = open_reset_test &
next(g.open_state) = open_idle &
g.turn = software
:
0b2_00;
d_rive.transmit_state = transmit_update_queue &
!(
g.queue_head != 0d2_0 &
g.HW_MEMORY_OWN[g.queue_head] = 0b1_0
) &
g.queue_head = 0b2_00 &
g.turn = software
:
0b2_00;
d_rive.transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full &
!d_rive.TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL &
g.HDP = 0b2_00 &
g.turn = software
:
g.HW_MEMORY_START;
d_rive.transmit_state = transmit_check_mis_queue &
g.turn = software
:
g.new_bd;
--CHANGE: This will never happen because stop update g.queue_ doesnt exist. Removing.
--stop_state = stop_update_queue &
--next(stop_state) = stop_idle &
--g.turn = software: 0b2_00;
TRUE: g.queue_tail;
esac;
#define BP_MEM_TRANSITION(index) \
next(g.HW_MEMORY_BP[index]) := case \
g.new_bd = uwconst(index, 2) & \
d_rive.transmit_state = transmit_updated_new_bd & \
g.turn = software \
: \
g.pa; \
\
/* special case for g.HW_MEMORY_START (1) */ \
index = 1 & \
d_rive.transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full & \
!d_rive.TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL & \
g.HDP = 0b2_00 & \
g.turn = software \
: \
g.pa; \
\
TRUE: g.HW_MEMORY_BP[index]; \
esac;
BP_MEM_TRANSITION(0)
BP_MEM_TRANSITION(1)
BP_MEM_TRANSITION(2)
BP_MEM_TRANSITION(3)
#undef BP_MEM_TRANSITION
#define NDP_MEM_TRANSITION(index) \
next(g.HW_MEMORY_NDP[index]) := case \
g.queue_tail = uwconst(index, 2) & \
d_rive.transmit_state = transmit_updated_new_bd & \
g.turn = software \
: \
g.new_bd; \
\
g.new_bd = uwconst(index, 2) & \
d_rive.transmit_state = transmit_updated_new_bd & \
g.turn = software \
: \
g.new_bd; \
\
index = 1 & \
d_rive.transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full & \
!d_rive.TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL & \
g.HDP = 0b2_00 & \
g.turn = software \
: \
0b2_00; \
\
TRUE: g.HW_MEMORY_NDP[index]; \
esac;
NDP_MEM_TRANSITION(0)
NDP_MEM_TRANSITION(1)
NDP_MEM_TRANSITION(2)
NDP_MEM_TRANSITION(3)
#undef NDP_MEM_TRANSITION
------------ ------------ ------------ ------------ ------------ ------------
-- TODO I wanst to replace this with a TRANS
------------ ------------ ------------ ------------ ------------ ------------
#define BL_TRANSITION(index) \
next(g.HW_MEMORY_BL[index]) := case \
g.new_bd = uwconst(index, 2) & \
d_rive.transmit_state = transmit_updated_new_bd & \
g.turn = software: \
g.length; \
\
g.turn = software & \
d_rive.transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full & \
!d_rive.TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL & \
g.HDP = 0b2_00: \
g.length; \
\
TRUE: g.HW_MEMORY_BL[index]; \
esac;
BL_TRANSITION(0)
BL_TRANSITION(1)
BL_TRANSITION(2)
BL_TRANSITION(3)
------------ ------------ ------------ ------------ ------------ ------------
------------ ------------ ------------ ------------ ------------ ------------
-- TODO I wanst to replace this with a TRANS
------------ ------------ ------------ ------------ ------------ ------------
#define OWN_TRANSITION(index) \
next(g.HW_MEMORY_OWN[index]) := case \
g.turn = HW_tx & \
g.HDP = uwconst(index, 2) & \
t_smit.tx_state = tx_setting_eoq_or_releasing_bd & \
g.HW_MEMORY_NDP[g.HDP] != 0b2_00: \
0b1_1; \
\
g.turn = HW_tx & \
t_smit.tx_state = tx_releasing_bd & \
g.HDP = 0d2_0: \
0b1_0; \
\
g.turn = HW_td & \
t_smit.td_state = td_releasing_bd & \
g.HDP = 0d2_0: \
0b1_0; \
\
g.turn = software & \
d_rive.transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full & \
!d_rive.TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL & \
g.HDP = 0b2_00 : \
g.HW_MEMORY_OWN[1]; \
\
TRUE: g.HW_MEMORY_OWN[index]; \
esac;
OWN_TRANSITION(0)
OWN_TRANSITION(1)
OWN_TRANSITION(2)
OWN_TRANSITION(3)
#undef OWN_TRANSITION
------------ ------------ ------------ ------------ ------------ ------------
#define EOQ_TRANSITION(index) \
next(g.HW_MEMORY_EOQ[index]) := case \
g.turn = software & \
g.new_bd = uwconst(index, 2) & \
d_rive.transmit_state = transmit_updated_new_bd \
: \
0b1_0; \
\
g.HDP = uwconst(index, 2) & \
t_smit.tx_state = tx_setting_eoq_or_releasing_bd & \
g.HW_MEMORY_NDP[g.HDP] = 0b2_00 & \
g.turn = HW_tx \
: \
0b1_1; \
\
g.turn = HW_td & \
g.HDP = uwconst(index, 2) & \
t_smit.td_state = td_waiting_for_tx & \
t_smit.tx_state = tx_idle & \
g.HDP != 0b2_00 \
: \
0b1_1; \
\
g.turn = software & \
uwconst(index, 2) = 0b2_01 & \
d_rive.transmit_state = transmit_bad_buffer_or_queue_full_or_not_queue_full & \
!d_rive.TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL & \
g.HDP = 0b2_00 \
: \
0b1_0; \
\
TRUE: g.HW_MEMORY_EOQ[index]; \
esac;
EOQ_TRANSITION(0)
EOQ_TRANSITION(1)
EOQ_TRANSITION(2)
EOQ_TRANSITION(3)
#undef EOQ_TRANSITION
INVAR
--A reset operation must not be initiated during an ongoing ini-
--tialization, transmission or tear down.
--(g.RESET = 0b1_0 | (g.RESET = 0b1_1 & t_smit.it_state = it_idle
-- & t_smiti.tx_state = tx_idle
-- & t_smit.td_state = td_idle)) &
-- CHANGE: we require that g.pa does not start at 0 or 3
g.pa != 0d2_0 & -- g.pa != 0d2_3 &
-- CHANGE: can we do this?
g.length != 0d2_0 &
!(g.length = 0d2_2 & g.pa = 0d2_2 ) &
!(g.pa + g.length < g.pa) &
--If the transmitter is resetting itself, then the transmitter does not
--transmit nor performs a tear down.
--CHNG (g.RESET = 0d1_0 | (t_smit.tx_state = td_idle & g.TEARDOWN = 0d1_0)) &
-- No wrong states allowed
--CHNG !d_rive.TRANSMIT_BAD_BUFFER_OR_QUEUE_FULL & !t_smit.TX_BUFFER_OVERFLOW &
-g.HW_MEMORY_BP[0] != 0b2_00 &
--g.HW_MEMORY_BP[1] != 0b2_00 &
--g.HW_MEMORY_BP[2] != 0b2_00 &
--g.HW_MEMORY_BP[3] != 0b2_00 &
-- Next 4 lines should be removed debugging
--g.HW_MEMORY_BP[0] != 0b2_10 &
--g.HW_MEMORY_BP[1] != 0b2_10 &
--g.HW_MEMORY_BP[2] != 0b2_10 &
--g.HW_MEMORY_BP[3] != 0b2_10 &
--g.HW_MEMORY_BP[0] != 0b2_11 &
--g.HW_MEMORY_BP[1] != 0b2_11 &
--g.HW_MEMORY_BP[2] != 0b2_11 &
--g.HW_MEMORY_BP[3] != 0b2_11
TRUE;
--A reset operation must not be initiated during an ongoing initialization, transmission or tear down.
--CHNG (g.RESET = 0d1_0 | (t_smit.tx_state = tx_idle & t_smit.td_state = td_idle & t_smit.it_state = it_idle))
TRANS
-- CHANGE: g.pa and lenght of msg does not change during transmission
--GHNG (t_smit.tx_state = tx_idle | (g.pa = next(g.pa) & g.length = next(g.length))) &
-- We only change PA and g.length when we start to transmit
--GHNG ((g.pa = next(g.pa) & g.length = next(g.length)) | next(t_smit.tx_state != tx_idle)) &
--Writing g.HDP when initialization, transmission or teardown are not idle, is an error.
--GHNG (g.HDP = next(g.HDP) | (t_smit.tx_state = tx_idle & t_smit.it_state = it_idle & t_smit.td_state = td_idle)) &
--Writing g.TEARDOWN during initialization or teardown is an error.
--GHNG (g.TEARDOWN = next(g.TEARDOWN) | (t_smit.it_state = it_idle & t_smit.td_state = td_idle));
(
d_rive.transmit_state = transmit_idle &
next(d_rive.transmit_state) != transmit_idle
)
|
(
g.pa = next(g.pa) &
g.length = next(g.length)
) &
TRUE;
-----------------------------------------------------------------------------------------
-- 4.6 Checking correctness
-----------------------------------------------------------------------------------------
---------------
--It is always possible for the model to sooner or later make transitions
--that describe the operations of open(), transmit(), and stop().
---------------
SPEC NAME dr_open_can_always_start := AG EF (g.open_state != open_idle );
SPEC NAME dr_transmit_always_can_start := AG EF (d_rive.transmit_state != transmit_idle );
SPEC NAME dr_stop_can_always_start := AG EF (d_rive.stop_state != stop_idle);
SPEC AG EF (g.open_state = open_idle );
SPEC AG EF (d_rive.transmit_state = transmit_idle );
SPEC AG EF (d_rive.stop_state = stop_idle);
---------------
--It is always possible for the model to sooner or later make transitions
--that describe the initialization, transmission and tear down operations
--of the transmitter.
---------------
-- can visit all checkpoints
SPEC EF(t_smit.it_state = it_resetting);
SPEC EF(t_smit.it_state = it_waiting_hdp);
SPEC EF(t_smit.td_state = td_waiting_for_tx);
SPEC EF(t_smit.td_state = td_releasing_bd);
SPEC EF(t_smit.td_state = td_clearing_td);
SPEC NAME tx_can_start := EF(t_smit.tx_state = tx_fetching_bd);
SPEC EF(t_smit.tx_state = tx_reading_memory);
SPEC EF(t_smit.tx_state = tx_releasing_bd);
SPEC EF(t_smit.td_state = td_waiting_for_tx);
--Can start the subroutines at all
SPEC AG EF (t_smit.it_state != it_idle );
SPEC AG EF (t_smit.tx_state != tx_idle );
SPEC AG EF (t_smit.td_state != td_idle );
SPEC AG EF (t_smit.it_state = it_idle );
SPEC AG EF (t_smit.tx_state = tx_idle );
SPEC AG EF (t_smit.td_state = td_idle );
---------------
--open(), transmit(), stop() cannot be executed simultaneously.
---------------
SPEC AG(
(g.open_state != open_idle)
->
d_rive.transmit_state = transmit_idle &
d_rive.stop_state = stop_idle
);
SPEC AG(
d_rive.transmit_state != transmit_idle
-> g.open_state = open_idle &
d_rive.stop_state = stop_idle
);
SPEC AG(
d_rive.stop_state != stop_idle
-> g.open_state = open_idle &
d_rive.transmit_state = transmit_idle
);
---------------
--If the transmitter is resetting itself, then the transmitter does not
--transmit nor performs a tear down.
---------------
SPEC NAME problem := AG(
g.RESET = 0d1_1
->
t_smit.tx_state = tx_idle &
t_smit.td_state = td_idle &
g.TEARDOWN = 0d1_0
);
---------------
--If the transmitter transmits, then the transmitter is not performing a
--reset.
---------------
SPEC AG(t_smit.td_state != td_idle -> g.RESET = 0d1_0);