socfpga_cyclone5.dtsi

/*
 * Copyright Altera Corporation (C) 2012,2014. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/dts-v1/;
/* First 4KB has trampoline code for secondary cores. */
/memreserve/ 0x00000000 0x0001000;
#include "socfpga.dtsi"

/ {
	soc {
		clkmgr@ffd04000 {
			clocks {
				osc1 {
					clock-frequency = <25000000>;
				};
			};
		};

		mmc0: dwmmc0@ff704000 {
			num-slots = <1>;
			broken-cd;
			bus-width = <4>;
			cap-mmc-highspeed;
			cap-sd-highspeed;
		};

		ethernet@ff702000 {
			phy-mode = "rgmii";
			phy-addr = <0xffffffff>; /* probe for phy addr */
			status = "okay";
		};

		sysmgr@ffd08000 {
			cpu1-start-addr = <0xffd080c4>;
		};

		hps_0_bridges: bridge@0xc0000000 {
			compatible = "altr,bridge-20.1", "simple-bus";
			reg = <0xc0000000 0x20000000>,
				<0xff200000 0x00200000>;
			reg-names = "axi_h2f", "axi_h2f_lw";
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0x00000001 0x00000000 0xff200000 0x00040000>;

			mm_bridge_0: bridge@0x100000000 {
				compatible = "ALTR,avalon-20.1", "simple-bus";
				reg = <0x00000001 0x00000000 0x00040000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x00002000 0x00000001 0x00002000 0x00000008>,
					<0x00030000 0x00000001 0x00030000 0x00000100>,
					<0x00003000 0x00000001 0x00003000 0x00000010>,
					<0x00001000 0x00000001 0x00001000 0x00000008>,
					<0x00004000 0x00000001 0x00004000 0x00000010>,
					<0x00005000 0x00000001 0x00005000 0x00000010>;

				jtag_uart: serial@0x2000 {
					compatible = "altr,juart-20.1", "altr,juart-1.0";
					reg = <0x00002000 0x00000008>;
					interrupts = <0 42 4>;
				}; //end serial@0x2000 (jtag_uart)

				ILC: ilc@0x30000 {
					compatible = "altr,altera_ilc-20.1", "altr,ilc-1.0";
					reg = <0x00030000 0x00000100>;
					interrupts = <0 42 4 0 41 1 0 40 1>;
					interrupt-names = "jtag_uart", "button_pio", "dipsw_pio";
					interrupt-controller;
					#interrupt-cells = <1>;
					altr,sw-fifo-depth = <32>;	/* embeddedsw.dts.params.altr,sw-fifo-depth type NUMBER */
				}; //end ilc@0x30000 (ILC)

				MyPIO_0: unknown@0x3000 {
					compatible = "unknown,unknown-1.0";
					reg = <0x00003000 0x00000010>;
				}; //end unknown@0x3000 (MyPIO_0)

				sysid_qsys: sysid@0x1000 {
					compatible = "altr,sysid-20.1", "altr,sysid-1.0";
					reg = <0x00001000 0x00000008>;
					id = <2899645186>;	/* embeddedsw.dts.params.id type NUMBER */
					timestamp = <1622044016>;	/* embeddedsw.dts.params.timestamp type NUMBER */
				}; //end sysid@0x1000 (sysid_qsys)

				dipsw_pio: gpio@0x4000 {
					compatible = "altr,pio-20.10", "altr,pio-1.0";
					reg = <0x00004000 0x00000010>;
					interrupts = <0 40 1>;
					altr,gpio-bank-width = <4>;	/* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */
					altr,interrupt-type = <3>;	/* embeddedsw.dts.params.altr,interrupt-type type NUMBER */
					altr,interrupt_type = <3>;	/* embeddedsw.dts.params.altr,interrupt_type type NUMBER */
					edge_type = <2>;	/* embeddedsw.dts.params.edge_type type NUMBER */
					level_trigger = <0>;	/* embeddedsw.dts.params.level_trigger type NUMBER */
					resetvalue = <0>;	/* embeddedsw.dts.params.resetvalue type NUMBER */
					#gpio-cells = <2>;
					gpio-controller;
				}; //end gpio@0x4000 (dipsw_pio)

				button_pio: gpio@0x5000 {
					compatible = "altr,pio-20.1", "altr,pio-1.0";
					reg = <0x00005000 0x00000010>;
					interrupts = <0 41 1>;
					altr,gpio-bank-width = <2>;	/* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */
					altr,interrupt-type = <2>;	/* embeddedsw.dts.params.altr,interrupt-type type NUMBER */
					altr,interrupt_type = <2>;	/* embeddedsw.dts.params.altr,interrupt_type type NUMBER */
					edge_type = <1>;	/* embeddedsw.dts.params.edge_type type NUMBER */
					level_trigger = <0>;	/* embeddedsw.dts.params.level_trigger type NUMBER */
					resetvalue = <0>;	/* embeddedsw.dts.params.resetvalue type NUMBER */
					#gpio-cells = <2>;
					gpio-controller;
				}; //end gpio@0x5000 (button_pio)
			}; //end bridge@0x100000000 (mm_bridge_0)
		}; //end bridge@0xc0000000 (hps_0_bridges)
	};
};

&watchdog0 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&i2c0 {
	status = "okay";
	speed-mode = <0>;
	adxl345@0 {
		compatible = "adxl34x";
		reg = <0x53>;
		interrupt-parent = <&portc>;
		interrupts = <3 2>;
	};
};