[RISCV] Support for ESP32-P4 instructions in RISCV backend

Author: sstefan1

.gitignore

@@ -73,3 +73,4 @@ pythonenv*
 /clang/utils/analyzer/projects/*/RefScanBuildResults
 # automodapi puts generated documentation files here.
 /lldb/docs/python_api/
+/dbg

.gitlab-ci.yml

@@ -186,7 +186,7 @@ build_and_test:
         [ ! -f "${BUILD_DIR}/lld-tests.log" ] || grep -i "internal compiler error\|Killed" ${BUILD_DIR}/lld-tests.log || true
       fi
   script:
-    - BUILD_PATH=$PWD/${BUILD_DIR}
+    - export BUILD_PATH=$PWD/${BUILD_DIR}
     - mkdir -p ${BUILD_PATH}
     - cmake -G Ninja
       -S llvm
@@ -209,6 +209,29 @@ build_and_test:
     - runuser -u test_runner -- ninja -C ${BUILD_PATH} check-lld 2>&1 > ${BUILD_PATH}/lld-tests.log;
     - chown -R ${CUR_USER} ${BUILD_PATH};
 
+test_xesppie:
+  stage: test
+  dependencies:
+    - pack_x86_64-linux-gnu
+  when: manual
+  allow_failure: true
+  only:
+    - tags
+  script:
+    - cd ${DIST_DIR}/
+    - ls -l
+    - DISTRO_PACK_FILE=$(cat dist_name_x86_64-linux-gnu)
+    - tar -xf ${DISTRO_PACK_FILE} 
+    - ls -l
+    - cd esp-clang
+    - ls -l
+    - pwd
+    - export CC="$(pwd)/bin/clang"
+    - export OBJDUMP="$(pwd)/bin/llvm-objdump"
+    - git clone -q --depth=1 "${GITLAB_SSH_SERVER}/idf/esp-compiler-tests.git"
+    - cd esp-compiler-tests/build-only/xesppie
+    - ./test_xesppie.py
+
 .build_linux-gnu_template:
   extends: .build_toolchain_template
   variables:
@@ -441,6 +464,7 @@ upload_to_github:
     - job: pack_x86_64-w64-mingw32
     - job: sign_x86_64-apple-darwin
     - job: sign_aarch64-apple-darwin
+    - job: test_xesppie
   before_script: []
   script:
     - ls -l ${DIST_DIR}

clang/include/clang/Basic/BuiltinsRISCV.def

@@ -89,5 +89,7 @@ TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")
 TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl")
 TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl")
 
+#include "clang/Basic/BuiltinsRISCVESP32P4.def"
+
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/include/clang/Basic/BuiltinsRISCVESP32P4.def

@@ -81,15 +81,15 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}}
+// RISCV32-NEXT: note: valid target CPU values are: esp32p4, generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
 // RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV32-NEXT: note: valid target CPU values are: esp32p4, generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'

clang/test/CodeGen/RISCV/riscv-esp32p4.c

@@ -1889,3 +1889,7 @@ let TargetPrefix = "riscv" in {
 include "llvm/IR/IntrinsicsRISCVXTHead.td"
 include "llvm/IR/IntrinsicsRISCVXsf.td"
 include "llvm/IR/IntrinsicsRISCVXCV.td"
+
+// Generated code
+// --------------
+include "llvm/IR/IntrinsicsRISCVESP32P4.td"

clang/test/Misc/target-invalid-cpu-note.c

@@ -71,6 +71,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
     {"xcvmac", {1, 0}},
     {"xcvmem", {1, 0}},
     {"xcvsimd", {1, 0}},
+    {"xesppie", {1, 0}},
     {"xsfvcp", {1, 0}},
     {"xsfvfnrclipxfqf", {1, 0}},
     {"xsfvfwmaccqqq", {1, 0}},

llvm/include/llvm/IR/IntrinsicsRISCV.td

@@ -442,6 +442,14 @@ struct RISCVOperand final : public MCParsedAsmOperand {
     }
   }
 
+  static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
+    if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
+      int64_t Value = CE->getValue();
+      return Value >= MinValue && Value <= MaxValue;
+    }
+    return false;
+  }
+
   bool isToken() const override { return Kind == KindTy::Token; }
   bool isReg() const override { return Kind == KindTy::Register; }
   bool isV0Reg() const {
@@ -467,6 +475,43 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   bool isRlist() const { return Kind == KindTy::Rlist; }
   bool isSpimm() const { return Kind == KindTy::Spimm; }
 
+  bool isImm(int64_t MinValue, int64_t MaxValue) const {
+    return Kind == KindTy::Immediate && inRange(getImm(), MinValue, MaxValue);
+  }
+
+  bool isImm8() const {
+    // The addi instruction maybe expaned to addmi and addi.
+    return isImm((-32768 - 128), (32512 + 127));
+  }
+
+  bool isSelect_2() const { return isImm(0, 1); }
+
+  bool isSelect_4() const { return isImm(0, 3); }
+
+  bool isSelect_8() const { return isImm(0, 7); }
+
+  bool isSelect_16() const { return isImm(0, 16); }
+
+  bool isOffset_16_16() const {
+    return isImm(-128, 112) &&
+           ((cast<MCConstantExpr>(getImm())->getValue() & 0xf) == 0);
+  }
+
+  bool isOffset_256_8() const {
+    return isImm(-1024, 1016) &&
+           ((cast<MCConstantExpr>(getImm())->getValue() & 0x7) == 0);
+  }
+
+  bool isOffset_256_16() const {
+    return isImm(-2048, 2032) &&
+           ((cast<MCConstantExpr>(getImm())->getValue() & 0xf) == 0);
+  }
+
+  bool isOffset_256_4() const {
+    return isImm(-512, 508) &&
+           ((cast<MCConstantExpr>(getImm())->getValue() & 0x3) == 0);
+  }
+
   bool isGPR() const {
     return Kind == KindTy::Register &&
            RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
@@ -841,6 +886,54 @@ struct RISCVOperand final : public MCParsedAsmOperand {
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isUImm9() const {
+    if (!isImm())
+      return false;
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<9>(Imm) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
+  bool isUImm10() const {
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    int64_t Imm;
+    bool IsValid;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    if (!IsConstantImm)
+      IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK);
+    else
+      IsValid = isUInt<10>(fixImmediateForRV32(Imm, isRV64Imm()));
+    return IsValid && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
+  bool isUImm12() const {
+    if (!isImm())
+      return false;
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    return IsConstantImm && isUInt<12>(Imm) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
+  bool isUImm13() const {
+    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+    int64_t Imm;
+    bool IsValid;
+    if (!isImm())
+      return false;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+    if (!IsConstantImm)
+      IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK);
+    else
+      IsValid = isUInt<13>(fixImmediateForRV32(Imm, isRV64Imm()));
+    return IsValid && VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImm10Lsb00NonZero() const {
     if (!isImm())
       return false;
@@ -1533,6 +1626,10 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, -(1 << 11), (1 << 11) - 32,
         "immediate must be a multiple of 32 bytes in the range");
+  case Match_InvalidUImm12:
+    return generateImmOutOfRangeError(
+        Operands, ErrorInfo, 0, (1 << 12) - 1,
+        "immediate must be in the range");  
   case Match_InvalidSImm13Lsb0:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, -(1 << 12), (1 << 12) - 2,

llvm/include/llvm/IR/IntrinsicsRISCVESP32P4.td

@@ -43,6 +43,7 @@ add_llvm_target(RISCVCodeGen
   RISCVInstrInfo.cpp
   RISCVISelDAGToDAG.cpp
   RISCVISelLowering.cpp
+  RISCVESP32P4ISelLowering.cpp
   RISCVMachineFunctionInfo.cpp
   RISCVMergeBaseOffset.cpp
   RISCVOptWInstrs.cpp