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The simulate function used to contaminate the input dut object, for example it added type information that was gathered from the simulation. Benefit of this was that after simulaton the same dut could be observed for changed values etc..
Downside was that since values in dut changed, it was not possible to run more than 1 simulation.
Because of this i changed the way how simulate works: now it makes a deepcopy of the input and uses that for simulation, thus the original dut stays untouched!
Now i need to add a convertToVHDL function that takes in a simulated object, for this i feel that the change should be reverted i.e. User can simulate the dut and then pass it to the convert.
Maybe there should be a flag dut._pyha_is_simulated that disables running successive simulations. Running simulation from non-default state can be major confusion.
The text was updated successfully, but these errors were encountered:
The
simulate
function used to contaminate the inputdut
object, for example it added type information that was gathered from the simulation. Benefit of this was that after simulaton the samedut
could be observed for changed values etc..Downside was that since values in
dut
changed, it was not possible to run more than 1 simulation.Because of this i changed the way how
simulate
works: now it makes a deepcopy of the input and uses that for simulation, thus the originaldut
stays untouched!Now i need to add a
convertToVHDL
function that takes in a simulated object, for this i feel that the change should be reverted i.e. User cansimulate
the dut and then pass it to theconvert
.Maybe there should be a flag
dut._pyha_is_simulated
that disables running successive simulations. Running simulation from non-default state can be major confusion.The text was updated successfully, but these errors were encountered: