Simulation: move to VHDL 93

[gasparka]

Current situation is that RTL simulations require VHDL 2008, but GATE simulation VHDL 93. Mostly everything in Pyha should work with 93.

Moving everything to 93 could make Pyha output more portable, i already know that Vivado needs to run in 93. Also doing everything in one standard is a simplification.

Potential problems:

1. Some code modifications required. E.g if bool should be converted to if bool = '1'.
2. 93 has no pre built fixed-point libaries in GHDL - probably just compile them manually in docker image.

[gasparka]

Harder than expected. Compiling fixed point libraries with GHDL not trivial. Managed to get somewhere but then get 'bound check' failure on runtime.
For now is stick with 2008.