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memory.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* Memory management
*
* (c) 1995 Bernd Schmidt
*/
#define DEBUG_STUPID 0
// don't touch
#define ACA500x_DEVELOPMENT 0
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "uae.h"
#include "uae/memory.h"
#include "rommgr.h"
#include "ersatz.h"
#include "zfile.h"
#include "custom.h"
#include "events.h"
#include "newcpu.h"
#include "autoconf.h"
#include "savestate.h"
#include "ar.h"
#include "crc32.h"
#include "gui.h"
#include "cdtv.h"
#include "akiko.h"
#include "arcadia.h"
#include "enforcer.h"
#include "threaddep/thread.h"
#include "gayle.h"
#include "debug.h"
#include "debugmem.h"
#include "gfxboard.h"
#include "cpuboard.h"
#include "uae/ppc.h"
#include "devices.h"
#include "inputdevice.h"
#include "casablanca.h"
#ifdef FSUAE // NL
#undef _WIN32
#endif
#ifdef FSUAE // NL
extern uae_u8 *natmem_offset, *natmem_offset_end;
#endif
bool canbang;
static bool rom_write_enabled;
#ifdef JIT
/* Set by each memory handler that does not simply access real memory. */
int special_mem;
#endif
static int mem_hardreset;
static bool roms_modified;
#define FLASHEMU 0
static bool isdirectjit (void)
{
return currprefs.cachesize && !currprefs.comptrustbyte;
}
static bool canjit (void)
{
if (currprefs.cpu_model < 68020 || currprefs.address_space_24)
return false;
return true;
}
static bool needmman (void)
{
if (!jit_direct_compatible_memory)
return false;
#ifdef _WIN32
#ifdef FSUAE
// FIXME: check if FS-UAE should return true here for Windows as well
#endif
return true;
#endif
if (canjit ())
return true;
return false;
}
static void nocanbang (void)
{
if (canbang) {
write_log(_T("Switching JIT direct off!\n"));
}
canbang = 0;
}
uae_u8 ce_banktype[65536];
uae_u8 ce_cachable[65536];
static size_t bootrom_filepos, chip_filepos, bogo_filepos, a3000lmem_filepos, a3000hmem_filepos, mem25bit_filepos;
/* Set if we notice during initialization that settings changed,
and we must clear all memory to prevent bogus contents from confusing
the Kickstart. */
static bool need_hardreset;
static int bogomem_aliasing;
/* The address space setting used during the last reset. */
static bool last_address_space_24;
addrbank *mem_banks[MEMORY_BANKS];
/* This has two functions. It either holds a host address that, when added
to the 68k address, gives the host address corresponding to that 68k
address (in which case the value in this array is even), OR it holds the
same value as mem_banks, for those banks that have baseaddr==0. In that
case, bit 0 is set (the memory access routines will take care of it). */
uae_u8 *baseaddr[MEMORY_BANKS];
#ifdef NO_INLINE_MEMORY_ACCESS
__inline__ uae_u32 longget (uaecptr addr)
{
return call_mem_get_func (get_mem_bank (addr).lget, addr);
}
__inline__ uae_u32 wordget (uaecptr addr)
{
return call_mem_get_func (get_mem_bank (addr).wget, addr);
}
__inline__ uae_u32 byteget (uaecptr addr)
{
return call_mem_get_func (get_mem_bank (addr).bget, addr);
}
__inline__ void longput (uaecptr addr, uae_u32 l)
{
call_mem_put_func (get_mem_bank (addr).lput, addr, l);
}
__inline__ void wordput (uaecptr addr, uae_u32 w)
{
call_mem_put_func (get_mem_bank (addr).wput, addr, w);
}
__inline__ void byteput (uaecptr addr, uae_u32 b)
{
call_mem_put_func (get_mem_bank (addr).bput, addr, b);
}
#endif
extern bool debugmem_initialized;
bool real_address_allowed(void)
{
return debugmem_initialized == false;
}
int addr_valid (const TCHAR *txt, uaecptr addr, uae_u32 len)
{
addrbank *ab = &get_mem_bank(addr);
if (ab == 0 || !(ab->flags & (ABFLAG_RAM | ABFLAG_ROM)) || addr < 0x100 || len > 16777215 || !valid_address (addr, len)) {
write_log (_T("corrupt %s pointer %x (%d) detected!\n"), txt, addr, len);
return 0;
}
return 1;
}
static int illegal_count;
/* A dummy bank that only contains zeros */
static uae_u32 REGPARAM3 dummy_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 dummy_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 dummy_bget (uaecptr) REGPARAM;
static void REGPARAM3 dummy_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 dummy_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 dummy_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 dummy_check (uaecptr addr, uae_u32 size) REGPARAM;
/* fake UAE ROM */
extern addrbank fakeuaebootrom_bank;
MEMORY_FUNCTIONS(fakeuaebootrom);
#define MAX_ILG 1000
#define NONEXISTINGDATA 0
//#define NONEXISTINGDATA 0xffffffff
static bool map_uae_boot_rom_direct(void)
{
if (!fakeuaebootrom_bank.allocated_size) {
fakeuaebootrom_bank.start = 0xf00000;
fakeuaebootrom_bank.reserved_size = 65536;
fakeuaebootrom_bank.mask = fakeuaebootrom_bank.reserved_size - 1;
if (!mapped_malloc (&fakeuaebootrom_bank))
return false;
// create jump table to real uae boot rom
for (int i = 0xff00; i < 0xfff8; i += 8) {
uae_u8 *p = fakeuaebootrom_bank.baseaddr + i;
p[0] = 0x4e;
p[1] = 0xf9;
uaecptr p2 = rtarea_base + i;
p[2] = p2 >> 24;
p[3] = p2 >> 16;
p[4] = p2 >> 8;
p[5] = p2 >> 0;
}
}
map_banks(&fakeuaebootrom_bank, 0xf0, 1, 1);
write_log(_T("Mapped fake UAE Boot ROM jump table.\n"));
return true;
}
// if access looks like old style hook call and f00000 space is unused, redirect to UAE boot ROM.
static bool maybe_map_boot_rom(uaecptr addr)
{
if (currprefs.uaeboard >= 2 && get_mem_bank_real(0xf00000) == &dummy_bank && !currprefs.mmu_model) {
uae_u32 pc = M68K_GETPC;
if (addr >= 0xf0ff00 && addr <= 0xf0fff8 && (((valid_address(pc, 2) && (pc < 0xf00000 || pc >= 0x01000000) && !currprefs.cpu_compatible) || (pc == addr && currprefs.cpu_compatible)))) {
bool check2 = currprefs.cpu_compatible;
if (!check2) {
uae_u32 w = get_word(pc);
// JSR xxxxxxxx or JSR (an)
if (w == 0x4eb9 || (w & 0xfff8) == 0x4e90)
check2 = true;
}
if (check2) {
if (map_uae_boot_rom_direct()) {
if (get_mem_bank_real(0xf00000) == &fakeuaebootrom_bank) {
return true;
}
}
}
}
}
return false;
}
static void dummylog (int rw, uaecptr addr, int size, uae_u32 val, int ins)
{
/* ignore Zorro3 expansion space */
if (addr >= AUTOCONFIG_Z3 && addr <= AUTOCONFIG_Z3 + 0x200)
return;
/* autoconfig and extended rom */
if (addr >= 0xe00000 && addr <= 0xf7ffff)
return;
/* motherboard ram */
if (addr >= 0x08000000 && addr <= 0x08000007)
return;
if (addr >= 0x07f00000 && addr <= 0x07f00007)
return;
if (addr >= 0x07f7fff0 && addr <= 0x07ffffff)
return;
if (debugmem_extinvalidmem(addr, val, rw ? size : -size))
return;
if ((illegal_count >= MAX_ILG && MAX_ILG > 0) && !memwatch_access_validator)
return;
if (MAX_ILG >= 0)
illegal_count++;
if (ins) {
write_log (_T("WARNING: Illegal opcode %cget at %08x PC=%x\n"),
size == 2 ? 'w' : 'l', addr, M68K_GETPC);
} else if (rw) {
write_log (_T("Illegal %cput at %08x=%08x PC=%x\n"),
size == 1 ? 'b' : size == 2 ? 'w' : 'l', addr, val, M68K_GETPC);
} else {
write_log (_T("Illegal %cget at %08x PC=%x\n"),
size == 1 ? 'b' : size == 2 ? 'w' : 'l', addr, M68K_GETPC);
}
}
// 250ms delay
static void gary_wait(uaecptr addr, int size, bool write)
{
static int cnt = 50;
#if 0
int lines = 313 * 12;
while (lines-- > 0)
x_do_cycles(228 * CYCLE_UNIT);
#endif
if (cnt > 0) {
write_log (_T("Gary timeout: %08x %d %c PC=%08x\n"), addr, size, write ? 'W' : 'R', M68K_GETPC);
cnt--;
}
}
static bool gary_nonrange(uaecptr addr)
{
if (currprefs.cs_fatgaryrev < 0)
return false;
if (addr < 0xb80000)
return false;
if (addr >= 0xd00000 && addr < 0xdc0000)
return true;
if (addr >= 0xdd0000 && addr < 0xde0000)
return true;
if (addr >= 0xdf8000 && addr < 0xe00000)
return false;
if (addr >= 0xe80000 && addr < 0xf80000)
return false;
return true;
}
void dummy_put (uaecptr addr, int size, uae_u32 val)
{
#if FLASHEMU
if (addr >= 0xf00000 && addr < 0xf80000 && size < 2)
flash_write(addr, val);
#endif
if (gary_nonrange(addr) || (size > 1 && gary_nonrange(addr + size - 1))) {
if (gary_timeout)
gary_wait (addr, size, true);
if (gary_toenb && currprefs.mmu_model)
exception2 (addr, true, size, regs.s ? 4 : 0);
}
}
static uae_u32 nonexistingdata(void)
{
if (currprefs.cs_unmapped_space == 1)
return 0x00000000;
if (currprefs.cs_unmapped_space == 2)
return 0xffffffff;
return NONEXISTINGDATA;
}
uae_u32 dummy_get_safe(uaecptr addr, int size, bool inst, uae_u32 defvalue)
{
uae_u32 v = defvalue;
uae_u32 mask = size == 4 ? 0xffffffff : (1 << (size * 8)) - 1;
if (currprefs.cpu_model >= 68040)
return v & mask;
if (!currprefs.cpu_compatible)
return v & mask;
if (currprefs.address_space_24)
addr &= 0x00ffffff;
if (addr >= 0x10000000)
return v & mask;
// CD32 and B2000
if (currprefs.cs_unmapped_space == 1)
return 0;
if (currprefs.cs_unmapped_space == 2)
return 0xffffffff & mask;
if ((currprefs.cpu_model <= 68010) || (currprefs.cpu_model == 68020 && (currprefs.chipset_mask & CSMASK_AGA) && currprefs.address_space_24)) {
if (size == 4) {
v = regs.db & 0xffff;
if (addr & 1)
v = (v << 8) | (v >> 8);
v = (v << 16) | v;
} else if (size == 2) {
v = regs.db & 0xffff;
if (addr & 1)
v = (v << 8) | (v >> 8);
} else {
v = regs.db;
v = (addr & 1) ? (v & 0xff) : ((v >> 8) & 0xff);
}
}
return v & mask;
}
uae_u32 dummy_get (uaecptr addr, int size, bool inst, uae_u32 defvalue)
{
uae_u32 v = defvalue;
#if FLASHEMU
if (addr >= 0xf00000 && addr < 0xf80000 && size < 2) {
if (addr < 0xf60000)
return flash_read(addr);
return 8;
}
#endif
#if ACA500x_DEVELOPMENT
if (addr == 0xb03000) {
return 0xffff;
}
if (addr == 0xb07000) {
return 0x0000;
}
if (addr == 0xb2f800) {
return 0xffff;
}
if (addr == 0xb3b800) {
return 0x0000;
}
if (addr == 0xb3f800) {
return currprefs.cpu_model > 68000 ? 0x0000 : 0xffff;
}
if (addr == 0xb0b000) {
return isideint() ? 0xffff : 0x0000;
}
#endif
if ((size == 2 || size == 4) && inst && maybe_map_boot_rom(addr)) {
if (size == 2)
return get_word(addr);
return get_long(addr);
}
if (gary_nonrange(addr) || (size > 1 && gary_nonrange(addr + size - 1))) {
if (gary_timeout)
gary_wait (addr, size, false);
if (gary_toenb)
exception2 (addr, false, size, (regs.s ? 4 : 0) | (inst ? 0 : 1));
return v;
}
return dummy_get_safe(addr, size, inst, defvalue);
}
static uae_u32 REGPARAM2 dummy_lget (uaecptr addr)
{
if (currprefs.illegal_mem)
dummylog (0, addr, 4, 0, 0);
return dummy_get (addr, 4, false, nonexistingdata());
}
uae_u32 REGPARAM2 dummy_lgeti (uaecptr addr)
{
if (currprefs.illegal_mem)
dummylog (0, addr, 4, 0, 1);
return dummy_get (addr, 4, true, nonexistingdata());
}
static uae_u32 REGPARAM2 dummy_wget (uaecptr addr)
{
if (currprefs.illegal_mem)
dummylog (0, addr, 2, 0, 0);
return dummy_get (addr, 2, false, nonexistingdata());
}
uae_u32 REGPARAM2 dummy_wgeti (uaecptr addr)
{
if (currprefs.illegal_mem)
dummylog (0, addr, 2, 0, 1);
return dummy_get (addr, 2, true, nonexistingdata());
}
static uae_u32 REGPARAM2 dummy_bget (uaecptr addr)
{
if (currprefs.illegal_mem)
dummylog (0, addr, 1, 0, 0);
return dummy_get (addr, 1, false, nonexistingdata());
}
static void REGPARAM2 dummy_lput (uaecptr addr, uae_u32 l)
{
if (currprefs.illegal_mem)
dummylog (1, addr, 4, l, 0);
dummy_put (addr, 4, l);
}
static void REGPARAM2 dummy_wput (uaecptr addr, uae_u32 w)
{
if (currprefs.illegal_mem)
dummylog (1, addr, 2, w, 0);
dummy_put (addr, 2, w);
}
static void REGPARAM2 dummy_bput (uaecptr addr, uae_u32 b)
{
if (currprefs.illegal_mem)
dummylog (1, addr, 1, b, 0);
dummy_put (addr, 1, b);
}
static int REGPARAM2 dummy_check (uaecptr addr, uae_u32 size)
{
return 0;
}
static void REGPARAM2 none_put (uaecptr addr, uae_u32 v)
{
}
static uae_u32 REGPARAM2 ones_get (uaecptr addr)
{
return 0xffffffff;
}
addrbank *get_sub_bank(uaecptr *paddr)
{
int i;
uaecptr addr = *paddr;
addrbank *ab = &get_mem_bank(addr);
struct addrbank_sub *sb = ab->sub_banks;
if (!sb)
return &dummy_bank;
for (i = 0; sb[i].bank; i++) {
int offset = addr & 65535;
if (offset < sb[i + 1].offset) {
uae_u32 mask = sb[i].mask;
uae_u32 maskval = sb[i].maskval;
if ((offset & mask) == maskval) {
*paddr = addr - sb[i].suboffset;
return sb[i].bank;
}
}
}
*paddr = addr - sb[i - 1].suboffset;
return sb[i - 1].bank;
}
uae_u32 REGPARAM3 sub_bank_lget (uaecptr addr) REGPARAM
{
addrbank *ab = get_sub_bank(&addr);
return ab->lget(addr);
}
uae_u32 REGPARAM3 sub_bank_wget(uaecptr addr) REGPARAM
{
addrbank *ab = get_sub_bank(&addr);
return ab->wget(addr);
}
uae_u32 REGPARAM3 sub_bank_bget(uaecptr addr) REGPARAM
{
addrbank *ab = get_sub_bank(&addr);
return ab->bget(addr);
}
void REGPARAM3 sub_bank_lput(uaecptr addr, uae_u32 v) REGPARAM
{
addrbank *ab = get_sub_bank(&addr);
ab->lput(addr, v);
}
void REGPARAM3 sub_bank_wput(uaecptr addr, uae_u32 v) REGPARAM
{
addrbank *ab = get_sub_bank(&addr);
ab->wput(addr, v);
}
void REGPARAM3 sub_bank_bput(uaecptr addr, uae_u32 v) REGPARAM
{
addrbank *ab = get_sub_bank(&addr);
ab->bput(addr, v);
}
uae_u32 REGPARAM3 sub_bank_lgeti(uaecptr addr) REGPARAM
{
addrbank *ab = get_sub_bank(&addr);
return ab->lgeti(addr);
}
uae_u32 REGPARAM3 sub_bank_wgeti(uaecptr addr) REGPARAM
{
addrbank *ab = get_sub_bank(&addr);
return ab->wgeti(addr);
}
int REGPARAM3 sub_bank_check(uaecptr addr, uae_u32 size) REGPARAM
{
addrbank *ab = get_sub_bank(&addr);
return ab->check(addr, size);
}
uae_u8 *REGPARAM3 sub_bank_xlate(uaecptr addr) REGPARAM
{
addrbank *ab = get_sub_bank(&addr);
return ab->xlateaddr(addr);
}
/* Chip memory */
static uae_u32 chipmem_full_mask;
static uae_u32 chipmem_full_size;
static int REGPARAM3 chipmem_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 chipmem_xlate (uaecptr addr) REGPARAM;
#ifdef AGA
/* AGA ce-chipram access */
static void ce2_timeout (void)
{
wait_cpu_cycle_read (0, -1);
}
static uae_u32 REGPARAM2 chipmem_lget_ce2 (uaecptr addr)
{
uae_u32 *m;
addr &= chipmem_bank.mask;
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
ce2_timeout ();
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 chipmem_wget_ce2 (uaecptr addr)
{
uae_u16 *m, v;
addr &= chipmem_bank.mask;
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
ce2_timeout ();
v = do_get_mem_word (m);
return v;
}
static uae_u32 REGPARAM2 chipmem_bget_ce2 (uaecptr addr)
{
addr &= chipmem_bank.mask;
ce2_timeout ();
return chipmem_bank.baseaddr[addr];
}
static void REGPARAM2 chipmem_lput_ce2 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr &= chipmem_bank.mask;
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
ce2_timeout ();
do_put_mem_long (m, l);
}
static void REGPARAM2 chipmem_wput_ce2 (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr &= chipmem_bank.mask;
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
ce2_timeout ();
do_put_mem_word (m, w);
}
static void REGPARAM2 chipmem_bput_ce2 (uaecptr addr, uae_u32 b)
{
addr &= chipmem_bank.mask;
ce2_timeout ();
chipmem_bank.baseaddr[addr] = b;
}
#endif
static uae_u32 REGPARAM2 chipmem_lget (uaecptr addr)
{
uae_u32 *m;
addr &= chipmem_bank.mask;
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_lget %08x = %08x\n", addr, do_get_mem_long (m));
#endif
#endif
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 chipmem_wget (uaecptr addr)
{
uae_u16 *m, v;
addr &= chipmem_bank.mask;
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
v = do_get_mem_word (m);
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_wget %08x = %08x\n", addr, v);
#endif
#endif
return v;
}
static uae_u32 REGPARAM2 chipmem_bget (uaecptr addr)
{
uae_u8 v;
addr &= chipmem_bank.mask;
v = chipmem_bank.baseaddr[addr];
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_wget %08x = %08x\n", addr, v);
#endif
#endif
return v;
}
void REGPARAM2 chipmem_lput (uaecptr addr, uae_u32 l)
{
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_lput %08x %08x\n", addr, l);
#endif
#endif
#ifdef FSUAE
#ifdef DEBUG_SYNC_MEMORY
write_sync_log("cl %08x %08x\n", addr, l);
#endif
#endif
uae_u32 *m;
addr &= chipmem_bank.mask;
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
do_put_mem_long (m, l);
}
void REGPARAM2 chipmem_wput (uaecptr addr, uae_u32 w)
{
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_wput %08x %08x\n", addr, w);
#endif
#endif
#ifdef FSUAE
#ifdef DEBUG_SYNC_MEMORY
write_sync_log("cw %08x %08x\n", addr, w);
#endif
#endif
uae_u16 *m;
addr &= chipmem_bank.mask;
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
do_put_mem_word (m, w);
}
void REGPARAM2 chipmem_bput (uaecptr addr, uae_u32 b)
{
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_bput %08x %08x\n", addr, b);
#endif
#endif
#ifdef FSUAE
#ifdef DEBUG_SYNC_MEMORY
write_sync_log("cb %08x %08x\n", addr, b);
#endif
#endif
addr &= chipmem_bank.mask;
chipmem_bank.baseaddr[addr] = b;
}
/* cpu chipmem access inside agnus addressable ram but no ram available */
static uae_u32 chipmem_dummy (void)
{
/* not really right but something random that has more ones than zeros.. */
return 0xffff & ~((1 << (uaerand () & 31)) | (1 << (uaerand () & 31)));
}
static void REGPARAM2 chipmem_dummy_bput (uaecptr addr, uae_u32 b)
{
}
static void REGPARAM2 chipmem_dummy_wput (uaecptr addr, uae_u32 b)
{
}
static void REGPARAM2 chipmem_dummy_lput (uaecptr addr, uae_u32 b)
{
}
static uae_u32 REGPARAM2 chipmem_dummy_bget (uaecptr addr)
{
return chipmem_dummy ();
}
static uae_u32 REGPARAM2 chipmem_dummy_wget (uaecptr addr)
{
return chipmem_dummy ();
}
static uae_u32 REGPARAM2 chipmem_dummy_lget (uaecptr addr)
{
return (chipmem_dummy () << 16) | chipmem_dummy ();
}
static uae_u32 REGPARAM2 chipmem_agnus_lget (uaecptr addr)
{
uae_u32 *m;
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size - 3)
return 0;
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_agnus_lget %08x = %08x\n", addr, do_get_mem_long (m));
#endif
#endif
return do_get_mem_long (m);
}
uae_u32 REGPARAM2 chipmem_agnus_wget (uaecptr addr)
{
uae_u16 *m;
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size - 1)
return 0;
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_agnus_lget %08x = %08x\n", addr, do_get_mem_word (m));
#endif
#endif
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 chipmem_agnus_bget (uaecptr addr)
{
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size)
return 0;
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_agnus_lget %08x = %08x\n", addr, chipmem_bank.baseaddr[addr]);
#endif
#endif
return chipmem_bank.baseaddr[addr];
}
static void REGPARAM2 chipmem_agnus_lput (uaecptr addr, uae_u32 l)
{
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_agnus_lput %08x %08x\n", addr, l);
#endif
#endif
uae_u32 *m;
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size - 3)
return;
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
do_put_mem_long (m, l);
}
void REGPARAM2 chipmem_agnus_wput (uaecptr addr, uae_u32 w)
{
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_agnus_wput %08x %08x\n", addr, w);
#endif
#endif
uae_u16 *m;
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size - 1)
return;
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
do_put_mem_word (m, w);
}
static void REGPARAM2 chipmem_agnus_bput (uaecptr addr, uae_u32 b)
{
#ifdef FSUAE
#ifdef DEBUG_MEM
write_log("chipmem_agnus_bput %08x %08x\n", addr, b);
#endif
#endif
addr &= chipmem_full_mask;
if (addr >= chipmem_full_size)
return;
chipmem_bank.baseaddr[addr] = b;
}
static int REGPARAM2 chipmem_check (uaecptr addr, uae_u32 size)
{
addr &= chipmem_bank.mask;
return (addr + size) <= chipmem_full_size;
}
static uae_u8 *REGPARAM2 chipmem_xlate (uaecptr addr)
{
addr &= chipmem_bank.mask;
return chipmem_bank.baseaddr + addr;
}
STATIC_INLINE void REGPARAM2 chipmem_lput_bigmem (uaecptr addr, uae_u32 v)
{
put_long (addr, v);
}
STATIC_INLINE void REGPARAM2 chipmem_wput_bigmem (uaecptr addr, uae_u32 v)
{
put_word (addr, v);
}
STATIC_INLINE void REGPARAM2 chipmem_bput_bigmem (uaecptr addr, uae_u32 v)
{
put_byte (addr, v);
}
STATIC_INLINE uae_u32 REGPARAM2 chipmem_lget_bigmem (uaecptr addr)
{
return get_long (addr);
}
STATIC_INLINE uae_u32 REGPARAM2 chipmem_wget_bigmem (uaecptr addr)
{
return get_word (addr);
}
STATIC_INLINE uae_u32 REGPARAM2 chipmem_bget_bigmem (uaecptr addr)
{
return get_byte (addr);
}
STATIC_INLINE int REGPARAM2 chipmem_check_bigmem (uaecptr addr, uae_u32 size)
{
return valid_address (addr, size);
}
STATIC_INLINE uae_u8* REGPARAM2 chipmem_xlate_bigmem (uaecptr addr)
{
return get_real_address (addr);
}
STATIC_INLINE void REGPARAM2 chipmem_lput_debugmem(uaecptr addr, uae_u32 v)
{
if (addr < debugmem_chiplimit)
debugmem_chiphit(addr, v, 4);
put_long(addr, v);
}
STATIC_INLINE void REGPARAM2 chipmem_wput_debugmem(uaecptr addr, uae_u32 v)
{
if (addr < debugmem_chiplimit)
debugmem_chiphit(addr, v, 2);
put_word(addr, v);
}
STATIC_INLINE void REGPARAM2 chipmem_bput_debugmem(uaecptr addr, uae_u32 v)
{
if (addr < debugmem_chiplimit)
debugmem_chiphit(addr, v, 1);
put_byte(addr, v);
}
STATIC_INLINE uae_u32 REGPARAM2 chipmem_lget_debugmem(uaecptr addr)
{
if (addr < debugmem_chiplimit)
return debugmem_chiphit(addr, 0, -4);
return get_long(addr);
}
STATIC_INLINE uae_u32 REGPARAM2 chipmem_wget_debugmem(uaecptr addr)
{
if (addr < debugmem_chiplimit)
return debugmem_chiphit(addr, 0, -2);
return get_word(addr);
}
STATIC_INLINE uae_u32 REGPARAM2 chipmem_bget_debugmem(uaecptr addr)
{
if (addr < debugmem_chiplimit)
return debugmem_chiphit(addr, 0, -1);
return get_byte(addr);
}
STATIC_INLINE int REGPARAM2 chipmem_check_debugmem(uaecptr addr, uae_u32 size)
{
return valid_address(addr, size);
}
STATIC_INLINE uae_u8* REGPARAM2 chipmem_xlate_debugmem(uaecptr addr)
{
return get_real_address(addr);
}
uae_u32 (REGPARAM2 *chipmem_lget_indirect)(uaecptr);
uae_u32 (REGPARAM2 *chipmem_wget_indirect)(uaecptr);
uae_u32 (REGPARAM2 *chipmem_bget_indirect)(uaecptr);
void (REGPARAM2 *chipmem_lput_indirect)(uaecptr, uae_u32);
void (REGPARAM2 *chipmem_wput_indirect)(uaecptr, uae_u32);
void (REGPARAM2 *chipmem_bput_indirect)(uaecptr, uae_u32);
int (REGPARAM2 *chipmem_check_indirect)(uaecptr, uae_u32);
uae_u8 *(REGPARAM2 *chipmem_xlate_indirect)(uaecptr);
void chipmem_setindirect(void)
{
if (debugmem_bank.baseaddr && debugmem_chiplimit) {
chipmem_lget_indirect = chipmem_lget_debugmem;
chipmem_wget_indirect = chipmem_wget_debugmem;
chipmem_bget_indirect = chipmem_bget_debugmem;
chipmem_lput_indirect = chipmem_lput_debugmem;
chipmem_wput_indirect = chipmem_wput_debugmem;
chipmem_bput_indirect = chipmem_bput_debugmem;
chipmem_check_indirect = chipmem_check_bigmem;
chipmem_xlate_indirect = chipmem_xlate_bigmem;
} else if (currprefs.z3chipmem_size) {
chipmem_lget_indirect = chipmem_lget_bigmem;
chipmem_wget_indirect = chipmem_wget_bigmem;
chipmem_bget_indirect = chipmem_bget_bigmem;
chipmem_lput_indirect = chipmem_lput_bigmem;
chipmem_wput_indirect = chipmem_wput_bigmem;
chipmem_bput_indirect = chipmem_bput_bigmem;
chipmem_check_indirect = chipmem_check_bigmem;
chipmem_xlate_indirect = chipmem_xlate_bigmem;
} else {
chipmem_lget_indirect = chipmem_lget;
chipmem_wget_indirect = chipmem_agnus_wget;
chipmem_bget_indirect = chipmem_agnus_bget;
chipmem_lput_indirect = chipmem_lput;
chipmem_wput_indirect = chipmem_agnus_wput;
chipmem_bput_indirect = chipmem_agnus_bput;
chipmem_check_indirect = chipmem_check;
chipmem_xlate_indirect = chipmem_xlate;
}
}
/* Slow memory */
MEMORY_FUNCTIONS(bogomem);
/* A3000 motherboard fast memory */
MEMORY_FUNCTIONS(a3000lmem);
MEMORY_FUNCTIONS(a3000hmem);
/* 25bit memory (0x01000000) */
MEMORY_FUNCTIONS(mem25bit);
/* debugger memory */
MEMORY_FUNCTIONS(debugmem);
MEMORY_WGETI(debugmem);
MEMORY_LGETI(debugmem);
/* Kick memory */
uae_u16 kickstart_version;
/*
* A1000 kickstart RAM handling
*
* RESET instruction unhides boot ROM and disables write protection
* write access to boot ROM hides boot ROM and enables write protection
*