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* Add local sel4twinkle-alloc crate for development * Add initial port of sel4twinkle-alloc * Enable app init function in the root task context * WIP vspace, working IPC, root task recieves notifications * Move fault handler in to application * Add internals to test 'vspace_new_ipc_buffer()' * Thread data contains mapped vaddr's to to IO with * Cleanup and README updates * Update README
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‎.gitignore

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/target
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**/*.rs.bk
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/artifacts
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src/bin/root-task.rs
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# tracked for now
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#src/bin/root-task.rs

‎Cargo.lock

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‎Cargo.toml

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#libsel4-sys = {git = "https://github.com/jonlamb-gh/libsel4-sys.git", branch = "devel"}
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libsel4-sys = {path = "libsel4-sys"}
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rlibc = "1.0"
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# TODO - move to a real repo
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sel4twinkle-alloc = {path = "sel4twinkle-alloc"}
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[dependencies.wee_alloc]
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version = "0.4"
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optional = true
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[features]
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default = []
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default = ["alloc"]
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alloc = ["wee_alloc"]
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test = ["alloc", "proptest"]

‎README.md

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The [Nitrogen6 SoloX][solox] SoC has both an A9 core and an M4 core.
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The seL4 root task runs on the A9 core.
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Here's a good [article][bd-article] that describes the platform.
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It first initializes the system, then runs a separate Rust application on the M4 core.
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See the [TRM][trm] for register details.
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## About the project
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The seL4 kernel, root-task and threads run on the A9 core.
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A bare metal Rust cortex-m project runs on the M4 core.
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- U-boot does initial bootstrapping of the A9 core and loads the master ELF binary
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- seL4 kernel is started on the A9 core
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- seL4 root task initializes some memory, devices and I/O for a thread
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- seL4 thread loads the M4 core firmware from the CPIO archive linked into the master ELF binary
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- seL4 thread starts up the M4 core and clock
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## Building
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** REQUIRES a cargo-fel4 that doesn't overwrite the root-task.rs **
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Note that the L2 cache memory is currently defined as OCRAM for the M4 core.
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Modify U-boot environment:
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# default loadaddr
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loadaddr=0x82000000
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# move it up a bit so we don't overlap with the elf-loader
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# move it up a bit so we don't overlap with the elf-loader, Rust binaries are big right now
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setenv loadaddr 0x83000000
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# boot alias command
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./scripts/apply-patches
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# a build.rs script is used to invoke the 'm4-firmware' project build
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# required because we can't have a normal dependency on a thing for a different target (A9/M4)
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cargo fel4 build
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```
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## Running
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On UART1 (U-boot/A9) console:
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```text
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U-Boot 2017.07-28767-g87d490f (Jun 20 2018 - 10:29:54 -0700)
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CPU: Freescale i.MX6SX rev1.3 at 792 MHz
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Reset cause: POR
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Board: nitrogen6sx
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I2C: ready
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DRAM: 1 GiB
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MMC: FSL_SDHC: 0, FSL_SDHC: 1
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SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB
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Display: lcd:1280x720M@60 (1280x720)
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In: serial
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Out: serial
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Err: serial
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Net: AR8035 at 4
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AR8035 at 5
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FEC0 [PRIME], FEC1, usb_ether
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Hit any key to stop autoboot: 0
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Using FEC0 device
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Filename 'feL4img'.
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Load address: 0x83000000
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Loading: #################################################################
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############################
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7.7 MiB/s
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done
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Bytes transferred = 1363524 (14ce44 hex)
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## Starting application at 0x83000000 ...
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ELF-loader started on CPU: ARM Ltd. Cortex-A9 r2p10
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paddr=[83000000..8315ffff]
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ELF-loading image 'kernel'
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paddr=[80000000..80032fff]
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vaddr=[e0000000..e0032fff]
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virt_entry=e0000000
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ELF-loading image 'root-task'
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paddr=[80033000..82080fff]
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vaddr=[10000..205dfff]
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virt_entry=10554
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Enabling MMU and paging
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Jumping to kernel-image entry point...
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Bootstrapping kernel
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Booting all finished, dropped to user space
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feL4 app init
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hello from a feL4 thread!
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SRC paddr = 0x20D8000 -- vaddr = 0x10000000
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CCM paddr = 0x20C4000 -- vaddr = 0x10001000
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TCM paddr = 0x7F8000 -- vaddr = 0x10002000
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created new CPIO reader
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Reader {
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archive_size: 3584,
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base_ptr: 0x00044010
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}
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parsed CPIO entry 'm4-firmware.bin'
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enabling M4 core clock
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copying M4 binary to TCM - 3044 bytes
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enabling and starting the M4 core
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waiting for SRC_SCR reset auto-clear (bit 3) to clear
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thread work all done, sitting on loop
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```
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On UART2 (M4) console:
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```text
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M4 core is up and running
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Hello world from Rust on Cortex-M4
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Hello world from Rust on Cortex-M4
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Hello world from Rust on Cortex-M4
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Hello world from Rust on Cortex-M4
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Hello world from Rust on Cortex-M4
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Hello world from Rust on Cortex-M4
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...
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```
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### A9 Test Deployment
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```bash
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tftp ${a9ocramloadaddr} ${serverip}:a9.bin
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go ${a9ocramloadaddr}
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```
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### M4 Test Deployment
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```bash
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tftp ${m4loadaddr} ${serverip}:m4.bin
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dcache flush
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bootaux ${m4loadaddr}
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```
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## Notes
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### L2 Cache
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seL4 is attempting to use the TCM region for L2 cache.
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Since we're using it for the M4 core, can we instead use the
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region at `0x009C_0000`; which is 256 KB, labeled as
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`L2 cache memory used as OCRAM aliased`?
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Could just be an issue with my config.
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L2 cache is configured as OCRAM by default I think.
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See Table 8-2 in the TRM, fuse `USE_L2_CACHE_AS_OCRAM BOOT_CFG2`.
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### Memory Map
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The i.MX6 SoloX has two cores with different address mapping.
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The ARM IP Bus (AIPS) memory map shows there is a `0x4000_0000` offset
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from the A9's address space to the M4's.
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Refer to Table 2-1 (System memory map) for Cortex-A9 core and
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to Table 2-2 (CM4 memory map) for Cortex-M4 of the i.MX6 SoloX
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reference ranual.
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To run Cortex-M4 it is needed to fill `TCM(L)`, that
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is addressed as `TCML ALIAS` (from zero).
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The same memory is mapped to `0x007f8000` of the
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Cortex-A9 (non-reflected in the Table 2-1).
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Note, this area is accessible by the Cortex-A9 after M4 clock
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is enabled in `CCM_CCGR3`.
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[solox]: https://boundarydevices.com/product/nit6_solox-imx6/
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[bd-article]: https://boundarydevices.com/using-the-cortex-m4-mcu-on-the-nit6_solox/
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[trm]: http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf
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[open-amp]: https://github.com/OpenAMP/open-amp/wiki

‎sel4twinkle-alloc/Cargo.toml

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[package]
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name = "sel4twinkle-alloc"
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version = "0.0.1"
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authors = ["jonlamb-gh <[email protected]>"]
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[dependencies]
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#libsel4-sys = {git = "https://github.com/jonlamb-gh/libsel4-sys.git", branch = "master"}
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libsel4-sys = {path = "../libsel4-sys"}

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