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26 | 26 | #include "llvm/CodeGen/LivePhysRegs.h"
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27 | 27 | #include "llvm/CodeGen/MachineFunctionPass.h"
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28 | 28 | #include "llvm/CodeGen/MachineRegisterInfo.h"
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| 29 | +#include "llvm/CodeGen/RegisterClassInfo.h" |
29 | 30 | #include "llvm/Support/Allocator.h"
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30 | 31 | #include "llvm/Support/Debug.h"
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31 | 32 | #include "llvm/Support/raw_ostream.h"
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@@ -137,6 +138,7 @@ class ExeDepsFix : public MachineFunctionPass {
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137 | 138 | MachineFunction *MF;
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138 | 139 | const TargetInstrInfo *TII;
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139 | 140 | const TargetRegisterInfo *TRI;
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| 141 | + RegisterClassInfo RegClassInfo; |
140 | 142 | std::vector<SmallVector<int, 1>> AliasMap;
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141 | 143 | const unsigned NumRegs;
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142 | 144 | LiveReg *LiveRegs;
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@@ -509,7 +511,8 @@ void ExeDepsFix::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
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509 | 511 | // max clearance or clearance higher than Pref.
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510 | 512 | unsigned MaxClearance = 0;
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511 | 513 | unsigned MaxClearanceReg = OriginalReg;
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512 |
| - for (auto Reg : OpRC->getRegisters()) { |
| 514 | + ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); |
| 515 | + for (auto Reg : Order) { |
513 | 516 | assert(AliasMap[Reg].size() == 1 &&
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514 | 517 | "Reg is expected to be mapped to a single index");
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515 | 518 | int RCrx = *regIndices(Reg).begin();
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@@ -785,6 +788,7 @@ bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
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785 | 788 | MF = &mf;
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786 | 789 | TII = MF->getSubtarget().getInstrInfo();
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787 | 790 | TRI = MF->getSubtarget().getRegisterInfo();
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| 791 | + RegClassInfo.runOnMachineFunction(mf); |
788 | 792 | LiveRegs = nullptr;
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789 | 793 | assert(NumRegs == RC->getNumRegs() && "Bad regclass");
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790 | 794 |
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