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[RISCV] Add fgtq.s and fgeq.s assembler aliases for Zfa.
We can swap operands and use fltq.s and fleq.s. Similar for D and H.
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llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

+24
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,30 @@ def FLTQ_H : FPCmp_rr<0b1010010, 0b101, "fltq.h", FPR16>;
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def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
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} // Predicates = [HasStdExtZfa, HasStdExtZfh]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZfa] in {
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def : InstAlias<"fgtq.s $rd, $rs, $rt",
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(FLTQ_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
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def : InstAlias<"fgeq.s $rd, $rs, $rt",
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(FLEQ_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
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}
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let Predicates = [HasStdExtZfa, HasStdExtD] in {
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def : InstAlias<"fgtq.d $rd, $rs, $rt",
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(FLTQ_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
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def : InstAlias<"fgeq.d $rd, $rs, $rt",
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(FLEQ_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
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}
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let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
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def : InstAlias<"fgtq.h $rd, $rs, $rt",
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(FLTQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
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def : InstAlias<"fgeq.h $rd, $rs, $rt",
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(FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
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}
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//===----------------------------------------------------------------------===//
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// Codegen patterns

llvm/test/MC/RISCV/zfa-valid.s

+33-3
Original file line numberDiff line numberDiff line change
@@ -176,10 +176,20 @@ fcvtmod.w.d a1, ft1, rtz
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# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
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fltq.s a1, fs1, fs2
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# CHECK-ASM-AND-OBJ: fleq.s a1, ft1, ft1
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# CHECK-ASM: encoding: [0xd3,0xc5,0x10,0xa0]
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# CHECK-ASM-AND-OBJ: fleq.s a1, ft1, ft2
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# CHECK-ASM: encoding: [0xd3,0xc5,0x20,0xa0]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
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fleq.s a1, ft1, ft1
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fleq.s a1, ft1, ft2
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# CHECK-ASM-AND-OBJ: fltq.s a1, fs2, fs1
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# CHECK-ASM: encoding: [0xd3,0x55,0x99,0xa0]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
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fgtq.s a1, fs1, fs2
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# CHECK-ASM-AND-OBJ: fleq.s a1, ft2, ft1
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# CHECK-ASM: encoding: [0xd3,0x45,0x11,0xa0]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
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fgeq.s a1, ft1, ft2
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# CHECK-ASM-AND-OBJ: fltq.d a1, fs1, fs2
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# CHECK-ASM: encoding: [0xd3,0xd5,0x24,0xa3]
@@ -191,6 +201,16 @@ fltq.d a1, fs1, fs2
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# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
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fleq.d a1, ft1, ft2
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# CHECK-ASM-AND-OBJ: fltq.d a1, fs2, fs1
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# CHECK-ASM: encoding: [0xd3,0x55,0x99,0xa2]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
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fgtq.d a1, fs1, fs2
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# CHECK-ASM-AND-OBJ: fleq.d a1, ft2, ft1
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# CHECK-ASM: encoding: [0xd3,0x45,0x11,0xa2]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
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fgeq.d a1, ft1, ft2
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# CHECK-ASM-AND-OBJ: fltq.h a1, fs1, fs2
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# CHECK-ASM: encoding: [0xd3,0xd5,0x24,0xa5]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
@@ -200,3 +220,13 @@ fltq.h a1, fs1, fs2
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# CHECK-ASM: encoding: [0xd3,0xc5,0x20,0xa4]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
202222
fleq.h a1, ft1, ft2
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# CHECK-ASM-AND-OBJ: fltq.h a1, fs2, fs1
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# CHECK-ASM: encoding: [0xd3,0x55,0x99,0xa4]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
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fgtq.h a1, fs1, fs2
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# CHECK-ASM-AND-OBJ: fleq.h a1, ft2, ft1
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# CHECK-ASM: encoding: [0xd3,0x45,0x11,0xa4]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
232+
fgeq.h a1, ft1, ft2

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