Factor out PCI configuration struct

Author: progbits

rust/src/e1000.rs

@@ -7,7 +7,7 @@ use crate::kernel::{ioapicenable, kalloc};
 use crate::mm::{PhysicalAddress, VirtualAddress, PAGE_SIZE};
 use crate::net::NetworkDevice;
 use crate::packet_buffer::PacketBuffer;
-use crate::pci;
+use crate::pci::PciConfig;
 
 const IRQ_PIC0: u32 = 0xB;
 
@@ -150,26 +150,38 @@ impl E1000 {
 
         // Enumerate the first four devices on the first PCI bus.
         // TODO: Move this out to a more generic PCI `probe` routine.
-        let mut target_device: Option<u32> = None;
+        let mut target_device: Option<PciConfig> = None;
         for device in 0..4 {
-            let device_addr: u32 = 0x80000000 | (device << 11);
-
-            // Read the vendor and device id of the current device.
-            let vendor_id = pci::read_vendor_id(device_addr);
-            let device_id = pci::read_device_id(device_addr);
-            if vendor_id == VENDOR_ID && device_id == DEVICE_ID {
-                target_device = Some(device);
-                break;
-            }
+            // Calculate the base address of the current device and load the
+            // PCI configuration struct for the device at the address.
+            let base_addr: u32 = 0x80000000 | (device << 11);
+            let pci_config = match PciConfig::new(base_addr) {
+                Ok(x) => {
+                    // Check if the device and vendor id match those of an
+                    // E1000 device.
+                    if x.vendor_id() != VENDOR_ID {
+                        continue;
+                    }
+                    if x.device_id() != DEVICE_ID {
+                        continue;
+                    }
+
+                    // Device is an E1000, stop searching.
+                    target_device = Some(x);
+                    break;
+                }
+                Err(_) => continue,
+            };
         }
 
         if target_device.is_none() {
             panic!("no network device\n\x00");
         }
 
-        // Configure the device command register and read the MMIO base register.
-        pci::set_bus_master(target_device.unwrap());
-        e1000.mmio_base = pci::read_bar(target_device.unwrap(), 0);
+        // Configure the device command register and read the first BAR
+        // register as the MMIO base register.
+        target_device.as_ref().unwrap().set_bus_master();
+        e1000.mmio_base = target_device.unwrap().bar(0);
 
         // Read the MAC address.
         // TODO: Lock EEPROM.
@@ -356,7 +368,8 @@ impl NetworkDevice for E1000 {
             } else if mask & InterruptMask::TXQE as u32 != 0 {
                 // cprint(b"e1000: tx queue empty\n\x00".as_ptr());
             } else if mask & InterruptMask::LSC as u32 != 0 {
-                // cprint(b"e1000: link status change seq error\n\x00".as_ptr());
+                // cprint(b"e1000: link status change seq
+                // error\n\x00".as_ptr());
             } else if mask & InterruptMask::RXSEQ as u32 != 0 {
                 // cprint(b"e1000: rx seq error\n\x00".as_ptr());
             } else if mask & InterruptMask::RXDMTO as u32 != 0 {

rust/src/pci.rs

@@ -4,8 +4,9 @@ use crate::asm::{in_dw, out_dw};
 const PCI_CONFIG_ADDR: u16 = 0xCF8;
 const PCI_CONFIG_DATA: u16 = 0xCFC;
 
-/// PCI configuration space header.
+/// Represents a PCI configuration space header.
 pub struct PciConfig {
+    base_addr: u32,
     vendor_id: u16,
     device_id: u16,
     command: u16,
@@ -19,56 +20,97 @@ pub struct PciConfig {
     bar: [u32; 6],
 }
 
-/// Read a PCI vendor identifier.
-pub unsafe fn read_vendor_id(base_addr: u32) -> u16 {
-    let mut result: u16 = 0x0;
-    for i in (0..=1).rev() {
-        out_dw(PCI_CONFIG_ADDR, base_addr | i);
-        let data = in_dw(PCI_CONFIG_DATA);
-        result |= (data as u16) << (i * 8);
+impl PciConfig {
+    /// Read a new PciConfig struct from a memory mapped I/O address.
+    pub fn new(base_addr: u32) -> Result<PciConfig, ()> {
+        unsafe {
+            let vendor_id = Self::read_vendor_id(base_addr);
+            let device_id = Self::read_device_id(base_addr);
+            let bar_0 = Self::read_bar(base_addr, 0);
+
+            Ok(PciConfig {
+                base_addr: base_addr,
+                vendor_id: vendor_id,
+                device_id: device_id,
+                command: 0,
+                status: 0,
+                revision_id: 0,
+                class_code: [0u8; 3],
+                cache_line_size: 0,
+                lat_timer: 0,
+                header_type: 0,
+                bist: 0,
+                bar: [bar_0, 0, 0, 0, 0, 0],
+            })
+        }
     }
-    result
-}
 
-/// Read a PCI device identifier.
-pub unsafe fn read_device_id(base_addr: u32) -> u16 {
-    let mut result: u16 = 0x0;
-    let mut j = 1;
-    for i in (2..=3).rev() {
-        out_dw(PCI_CONFIG_ADDR, base_addr | i);
-        let data = in_dw(PCI_CONFIG_DATA);
-        result |= (data as u16) << (j * 8);
-        j -= 1;
+    /// Return the vendor id associated with the device.
+    pub fn vendor_id(&self) -> u16 {
+        self.vendor_id
     }
-    result
-}
 
-/// Read the `n`th BAR register.
-pub unsafe fn read_bar(device: u32, _n: u8) -> u32 {
-    let mut result: u32 = 0x0;
-    let mut j = 3;
-    for i in (16..=19).rev() {
-        out_dw(PCI_CONFIG_ADDR, (0x80000000 | device << 11) | i);
-        let data = in_dw(PCI_CONFIG_DATA);
-        result |= data << (j * 8);
-        j -= 1;
+    /// Return the device id associated with the device.
+    pub fn device_id(&self) -> u16 {
+        self.device_id
+    }
+
+    /// Return the value of the ith base address register.
+    pub fn bar(&self, i: u8) -> u32 {
+        self.bar[i as usize]
     }
-    result
-}
 
-/// Setup the device as a bus master.
-pub unsafe fn set_bus_master(device: u32) {
-    let mut command: u32 = 0x0;
-    let mut j = 1;
-    for i in (4..=5).rev() {
-        out_dw(PCI_CONFIG_ADDR, (0x80000000 | device << 11) | i);
-        let data = in_dw(PCI_CONFIG_DATA);
-        command |= data << (j * 8);
-        j -= 1;
+    /// Set the device as a bus master.
+    pub unsafe fn set_bus_master(&self) {
+        let mut command: u32 = 0x0;
+        let mut j = 1;
+        for i in (4..=5).rev() {
+            out_dw(PCI_CONFIG_ADDR, self.base_addr | i);
+            let data = in_dw(PCI_CONFIG_DATA);
+            command |= data << (j * 8);
+            j -= 1;
+        }
+
+        // Set the bus master flag and write back the command register.
+        command |= 1 << 2;
+        out_dw(PCI_CONFIG_ADDR, self.base_addr | 4);
+        out_dw(PCI_CONFIG_DATA, command);
+    }
+
+    /// Read a PCI vendor identifier.
+    unsafe fn read_vendor_id(base_addr: u32) -> u16 {
+        let mut result: u16 = 0x0;
+        for i in (0..=1).rev() {
+            out_dw(PCI_CONFIG_ADDR, base_addr | i);
+            let data = in_dw(PCI_CONFIG_DATA);
+            result |= (data as u16) << (i * 8);
+        }
+        result
     }
 
-    // Set the bus master flag and write back the command register.
-    command |= 1 << 2;
-    out_dw(PCI_CONFIG_ADDR, (0x80000000 | device << 11) | 4);
-    out_dw(PCI_CONFIG_DATA, command);
+    /// Read a PCI device identifier.
+    unsafe fn read_device_id(base_addr: u32) -> u16 {
+        let mut result: u16 = 0x0;
+        let mut j = 1;
+        for i in (2..=3).rev() {
+            out_dw(PCI_CONFIG_ADDR, base_addr | i);
+            let data = in_dw(PCI_CONFIG_DATA);
+            result |= (data as u16) << (j * 8);
+            j -= 1;
+        }
+        result
+    }
+
+    /// Read the nth BAR register.
+    unsafe fn read_bar(base_addr: u32, _n: u32) -> u32 {
+        let mut result: u32 = 0x0;
+        let mut j = 3;
+        for i in (16..=19).rev() {
+            out_dw(PCI_CONFIG_ADDR, base_addr | i);
+            let data = in_dw(PCI_CONFIG_DATA);
+            result |= data << (j * 8);
+            j -= 1;
+        }
+        result
+    }
 }