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raskyrasky
committed
more conversions to Z logging
1 parent b85ffc7 commit d775aee

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9 files changed

+92
-82
lines changed

9 files changed

+92
-82
lines changed

‎backup.go

+13-13
Original file line numberDiff line numberDiff line change
@@ -38,11 +38,11 @@ func (b *HwBackupRam) tryAutoDetect(data []byte) bool {
3838

3939
if b.auxCntrWritten {
4040
b.addrSize = len(data) - 2
41-
modBackup.Warnf("autodetect addr size: %d", b.addrSize)
41+
modBackup.WarnZ("autodetect addr size").Int("size", b.addrSize).End()
4242
b.autodetect = false
4343
return true
4444
}
45-
modBackup.Infof("autodetect failed, waiting")
45+
modBackup.InfoZ("autodetect failed, waiting").End()
4646
return false
4747
}
4848

@@ -54,16 +54,16 @@ func (b *HwBackupRam) SpiTransfer(data []byte) ([]byte, spi.ReqStatus) {
5454
return nil, spi.ReqFinish
5555

5656
case 0x5: // RDSR
57-
modBackup.Infof("cmd RDSR")
57+
modBackup.InfoZ("cmd RDSR").End()
5858
return nil, spi.ReqFinish
5959

6060
case 0x4: // WRDI
61-
modBackup.Infof("cmd WRDI")
61+
modBackup.InfoZ("cmd WRDI").End()
6262
b.writeEnabled = false
6363
return nil, spi.ReqFinish
6464

6565
case 0x6: // WREN
66-
modBackup.Infof("cmd WREN")
66+
modBackup.InfoZ("cmd WREN").End()
6767
b.writeEnabled = true
6868
return nil, spi.ReqFinish
6969

@@ -84,7 +84,7 @@ func (b *HwBackupRam) SpiTransfer(data []byte) ([]byte, spi.ReqStatus) {
8484
}
8585
}
8686

87-
modBackup.WithField("addr", b.addr).Info("cmd RD")
87+
modBackup.InfoZ("cmd RD").Int("addr", b.addr).End()
8888
buf := make([]byte, 256)
8989
sz := len(b.sram) - b.addr
9090
if sz > 256 {
@@ -95,10 +95,10 @@ func (b *HwBackupRam) SpiTransfer(data []byte) ([]byte, spi.ReqStatus) {
9595

9696
case 0x2, 0xA: // WR
9797
if !b.writeEnabled {
98-
modBackup.Fatal("writing with write disabled")
98+
modBackup.FatalZ("writing with write disabled").End()
9999
}
100100
if b.autodetect {
101-
modBackup.Fatal("writing while autodetecting size")
101+
modBackup.FatalZ("writing while autodetecting size").End()
102102
}
103103

104104
if len(data) < 1+b.addrSize {
@@ -111,7 +111,7 @@ func (b *HwBackupRam) SpiTransfer(data []byte) ([]byte, spi.ReqStatus) {
111111
b.addr <<= 8
112112
b.addr |= int(v)
113113
}
114-
modBackup.WithField("addr", b.addr).Info("cmd WR")
114+
modBackup.InfoZ("cmd WR").Int("addr", b.addr).End()
115115
}
116116

117117
// Copy the whole buffer every time; I know it's inefficient,
@@ -150,9 +150,9 @@ func (b *HwBackupRam) SpiTransfer(data []byte) ([]byte, spi.ReqStatus) {
150150
// }
151151

152152
default:
153-
modBackup.Errorf("unimplemented command %x (len=%d)", data, len(data))
153+
modBackup.ErrorZ("unimplemented command").Blob("data", data).Int("len", len(data)).End()
154154
if len(data) == 16 {
155-
modBackup.Fatalf("ciao")
155+
modBackup.FatalZ("data too long").End()
156156
}
157157
return nil, spi.ReqContinue
158158
}
@@ -167,9 +167,9 @@ func (b *HwBackupRam) AuxSpiCntWritten(value uint16) {
167167
}
168168

169169
func (b *HwBackupRam) SpiBegin() {
170-
modBackup.Info("begin transfer")
170+
modBackup.InfoZ("begin transfer").End()
171171
}
172172

173173
func (b *HwBackupRam) SpiEnd() {
174-
modBackup.Info("end transfer")
174+
modBackup.InfoZ("end transfer").End()
175175
}

‎dma.go

+5-5
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ func (dma *HwDmaChannel) startEvent() DmaEvent {
8383
case 7:
8484
return DmaEventGxFifo
8585
default:
86-
log.ModDma.Fatalf("DMA start=%d not implemented", start)
86+
log.ModDma.FatalZ("DMA start not implemented").Uint16("event", start).End()
8787
return DmaEventInvalid
8888
}
8989
} else {
@@ -94,7 +94,7 @@ func (dma *HwDmaChannel) startEvent() DmaEvent {
9494
case 2:
9595
return DmaEventGamecard
9696
default:
97-
log.ModDma.Fatalf("DMA start=%d not implemented", start)
97+
log.ModDma.FatalZ("DMA start not implemented").Uint16("event", start).End()
9898
return DmaEventInvalid
9999
}
100100
}
@@ -139,7 +139,7 @@ func (dma *HwDmaChannel) xfer() {
139139
dinc := (ctrl >> 5) & 3
140140

141141
if sinc == 3 {
142-
log.ModDma.Fatal("sinc=3 should not happen")
142+
log.ModDma.FatalZ("sinc=3 should not happen").End()
143143
}
144144

145145
cnt := uint32(dma.DmaCount.Value)
@@ -239,7 +239,7 @@ func (dma *HwDmaChannel) xfer() {
239239

240240
func (dma *HwDmaChannel) TriggerEvent(event DmaEvent) {
241241
if event == DmaEventInvalid {
242-
log.ModDma.Fatalf("invalid DMA event triggered (?)")
242+
log.ModDma.FatalZ("invalid DMA event triggered (?)").End()
243243
}
244244

245245
if dma.inProgress {
@@ -251,7 +251,7 @@ func (dma *HwDmaChannel) TriggerEvent(event DmaEvent) {
251251
return
252252
}
253253
if dma.pendingEvent != DmaEventInvalid {
254-
log.ModDma.Fatalf("too many pending DMA events")
254+
log.ModDma.FatalZ("too many pending DMA events").End()
255255
}
256256
dma.pendingEvent = event
257257
} else {

‎emu/logger/entryz.go

+11
Original file line numberDiff line numberDiff line change
@@ -182,6 +182,17 @@ func (z *EntryZ) Vector12(key string, value [4]fixed.F12) *EntryZ {
182182
return z
183183
}
184184

185+
func (z *EntryZ) Blob(key string, value []byte) *EntryZ {
186+
if z != nil {
187+
f := &z.zfbuf[z.zfidx]
188+
f.Type = FieldTypeBlob
189+
f.Key = key
190+
f.Blob = value
191+
z.zfidx++
192+
}
193+
return z
194+
}
195+
185196
var logfuncs = []func(*logrus.Entry, ...interface{}){
186197
(*logrus.Entry).Panic,
187198
(*logrus.Entry).Fatal,

‎emu/logger/fields.go

+4
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ const (
2424
FieldTypeStringer
2525
FieldTypeFixed12
2626
FieldTypeVector12
27+
FieldTypeBlob
2728
)
2829

2930
type ZField struct {
@@ -39,6 +40,7 @@ type ZField struct {
3940
Vector12 [4]fixed.F12
4041
Interface interface{}
4142
Boolean bool
43+
Blob []byte
4244
}
4345

4446
func (f *ZField) Value() string {
@@ -72,6 +74,8 @@ func (f *ZField) Value() string {
7274
return f.Fixed12.String()
7375
case FieldTypeVector12:
7476
return fmt.Sprint(f.Vector12)
77+
case FieldTypeBlob:
78+
return fmt.Sprintf("%x", f.Blob)
7579
}
7680
return ""
7781
}

‎firmware.go

+6-11
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
package main
22

33
import (
4-
"fmt"
54
log "ndsemu/emu/logger"
65
"ndsemu/emu/spi"
76
"os"
@@ -57,9 +56,7 @@ func (ff *HwFirmwareFlash) SpiTransfer(data []byte) ([]byte, spi.ReqStatus) {
5756
}
5857
if len(data) == 4 {
5958
ff.addr = uint32(data[1])<<16 | uint32(data[2])<<8 | uint32(data[3])
60-
modFw.WithFields(log.Fields{
61-
"addr": fmt.Sprintf("%06x", ff.addr),
62-
}).Info("READ")
59+
modFw.InfoZ("HEAD").Hex32("addr", ff.addr).End()
6360
}
6461

6562
buf := make([]byte, 1024)
@@ -71,14 +68,14 @@ func (ff *HwFirmwareFlash) SpiTransfer(data []byte) ([]byte, spi.ReqStatus) {
7168
if ff.wen {
7269
status |= 2
7370
}
74-
modFw.WithField("val", fmt.Sprintf("%02x", status)).Info("read status")
71+
modFw.InfoZ("read status").Hex8("val", status).End()
7572
return []byte{status}, spi.ReqFinish
7673
case FFCodeWren:
77-
modFw.Info("write enabled")
74+
modFw.InfoZ("write enabled").End()
7875
ff.wen = true
7976
return nil, spi.ReqFinish
8077
case FFCodeWrdi:
81-
modFw.Info("write disabled")
78+
modFw.InfoZ("write disabled").End()
8279
ff.wen = false
8380
return nil, spi.ReqFinish
8481
case FFCodePw:
@@ -87,15 +84,13 @@ func (ff *HwFirmwareFlash) SpiTransfer(data []byte) ([]byte, spi.ReqStatus) {
8784
}
8885
if len(data) == 4 {
8986
ff.addr = uint32(data[1])<<16 | uint32(data[2])<<8 | uint32(data[3])
90-
modFw.WithFields(log.Fields{
91-
"addr": fmt.Sprintf("%06x", ff.addr),
92-
}).Info("WRITE")
87+
modFw.InfoZ("WRITE").Hex32("addr", ff.addr).End()
9388
}
9489
// Put away buffer data; will be written just once, in SpiEnd
9590
ff.wbuf = data[4:]
9691
return nil, spi.ReqContinue
9792
default:
98-
modFw.Errorf("unsupported command %02x", cmd)
93+
modFw.ErrorZ("unsupported command").Hex8("cmd", cmd).End()
9994
return nil, spi.ReqFinish
10095
}
10196
}

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