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bors[bot]Disasm
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Disasm
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Merge #31
31: Add more CSRs r=laanwj a=Disasm Co-authored-by: Vadim Kaushan <[email protected]>
2 parents 5a1ab83 + d3dc245 commit 7f1e4a5

28 files changed

+665
-74
lines changed

‎Cargo.toml

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
[package]
22
name = "riscv"
3-
version = "0.5.3"
3+
version = "0.5.4"
44
repository = "https://github.com/rust-embedded/riscv"
55
authors = ["The RISC-V Team <[email protected]>"]
66
categories = ["embedded", "hardware-support", "no-std"]

‎asm.S

+249-34
Original file line numberDiff line numberDiff line change
@@ -24,37 +24,252 @@ __sfence_vma:
2424
sfence.vma a0, a1
2525
ret
2626

27-
REG_READ_WRITE(fcsr, 0x003)
28-
REG_SET_CLEAR(fcsr, 0x003)
29-
30-
// M-mode registers
31-
REG_READ(mcause, 0x342)
32-
REG_READ(mcycle, 0xB00)
33-
REG_READ(mepc, 0x341)
34-
REG_READ(mie, 0x304)
35-
REG_SET_CLEAR(mie, 0x304)
36-
REG_READ(minstret, 0xB02)
37-
REG_READ(mip, 0x344)
38-
REG_READ(misa, 0x301)
39-
REG_READ_WRITE(mstatus, 0x300)
40-
REG_SET_CLEAR(mstatus, 0x300)
41-
REG_READ_WRITE(mtvec, 0x305)
42-
REG_READ(mvendorid, 0xF11)
43-
REG_READ(marchid, 0xF12)
44-
REG_READ(mimpid, 0xF13)
45-
REG_READ(mhartid, 0xF14)
46-
47-
// S-mode registers
48-
REG_READ_WRITE(satp, 0x180)
49-
REG_READ(scause, 0x142)
50-
REG_READ_WRITE(sepc, 0x141)
51-
REG_READ(sie, 0x104)
52-
REG_SET_CLEAR(sie, 0x104)
53-
REG_READ(sip, 0x144)
54-
REG_READ_WRITE(sscratch, 0x140)
55-
REG_READ_WRITE(sstatus, 0x100)
56-
REG_SET_CLEAR(sstatus, 0x100)
57-
REG_READ(stval, 0x143)
58-
REG_READ_WRITE(stvec, 0x105)
59-
60-
REG_READ(time, 0xC01)
27+
// User Trap Setup
28+
RW(0x000, ustatus) // User status register
29+
RW(0x004, uie) // User interrupt-enable register
30+
RW(0x005, utvec) // User trap handler base address
31+
32+
// User Trap Handling
33+
RW(0x040, uscratch) // Scratch register for user trap handlers
34+
RW(0x041, uepc) // User exception program counter
35+
RW(0x042, ucause) // User trap cause
36+
RW(0x043, utval) // User bad address or instruction
37+
RW(0x044, uip) // User interrupt pending
38+
39+
// User Floating-Point CSRs
40+
RW(0x001, fflags) // Floating-Point Accrued Exceptions
41+
RW(0x002, frm) // Floating-Point Dynamic Rounding Mode
42+
RW(0x003, fcsr) // Floating-Point Control and Status Register (frm + fflags)
43+
44+
// User Counter/Timers
45+
RO( 0xC00, cycle) // Cycle counter for RDCYCLE instruction
46+
RO( 0xC01, time) // Timer for RDTIME instruction
47+
RO( 0xC02, instret) // Instructions-retired counter for RDINSTRET instruction
48+
RO( 0xC03, hpmcounter3) // Performance-monitoring counter
49+
RO( 0xC04, hpmcounter4) // Performance-monitoring counter
50+
RO( 0xC05, hpmcounter5) // Performance-monitoring counter
51+
RO( 0xC06, hpmcounter6) // Performance-monitoring counter
52+
RO( 0xC07, hpmcounter7) // Performance-monitoring counter
53+
RO( 0xC08, hpmcounter8) // Performance-monitoring counter
54+
RO( 0xC09, hpmcounter9) // Performance-monitoring counter
55+
RO( 0xC0A, hpmcounter10) // Performance-monitoring counter
56+
RO( 0xC0B, hpmcounter11) // Performance-monitoring counter
57+
RO( 0xC0C, hpmcounter12) // Performance-monitoring counter
58+
RO( 0xC0D, hpmcounter13) // Performance-monitoring counter
59+
RO( 0xC0E, hpmcounter14) // Performance-monitoring counter
60+
RO( 0xC0F, hpmcounter15) // Performance-monitoring counter
61+
RO( 0xC10, hpmcounter16) // Performance-monitoring counter
62+
RO( 0xC11, hpmcounter17) // Performance-monitoring counter
63+
RO( 0xC12, hpmcounter18) // Performance-monitoring counter
64+
RO( 0xC13, hpmcounter19) // Performance-monitoring counter
65+
RO( 0xC14, hpmcounter20) // Performance-monitoring counter
66+
RO( 0xC15, hpmcounter21) // Performance-monitoring counter
67+
RO( 0xC16, hpmcounter22) // Performance-monitoring counter
68+
RO( 0xC17, hpmcounter23) // Performance-monitoring counter
69+
RO( 0xC18, hpmcounter24) // Performance-monitoring counter
70+
RO( 0xC19, hpmcounter25) // Performance-monitoring counter
71+
RO( 0xC1A, hpmcounter26) // Performance-monitoring counter
72+
RO( 0xC1B, hpmcounter27) // Performance-monitoring counter
73+
RO( 0xC1C, hpmcounter28) // Performance-monitoring counter
74+
RO( 0xC1D, hpmcounter29) // Performance-monitoring counter
75+
RO( 0xC1E, hpmcounter30) // Performance-monitoring counter
76+
RO( 0xC1F, hpmcounter31) // Performance-monitoring counter
77+
RO32(0xC80, cycleh) // Upper 32 bits of cycle, RV32I only
78+
RO32(0xC81, timeh) // Upper 32 bits of time, RV32I only
79+
RO32(0xC82, instreth) // Upper 32 bits of instret, RV32I only
80+
RO32(0xC83, hpmcounter3h) // Upper 32 bits of hpmcounter3, RV32I only
81+
RO32(0xC84, hpmcounter4h)
82+
RO32(0xC85, hpmcounter5h)
83+
RO32(0xC86, hpmcounter6h)
84+
RO32(0xC87, hpmcounter7h)
85+
RO32(0xC88, hpmcounter8h)
86+
RO32(0xC89, hpmcounter9h)
87+
RO32(0xC8A, hpmcounter10h)
88+
RO32(0xC8B, hpmcounter11h)
89+
RO32(0xC8C, hpmcounter12h)
90+
RO32(0xC8D, hpmcounter13h)
91+
RO32(0xC8E, hpmcounter14h)
92+
RO32(0xC8F, hpmcounter15h)
93+
RO32(0xC90, hpmcounter16h)
94+
RO32(0xC91, hpmcounter17h)
95+
RO32(0xC92, hpmcounter18h)
96+
RO32(0xC93, hpmcounter19h)
97+
RO32(0xC94, hpmcounter20h)
98+
RO32(0xC95, hpmcounter21h)
99+
RO32(0xC96, hpmcounter22h)
100+
RO32(0xC97, hpmcounter23h)
101+
RO32(0xC98, hpmcounter24h)
102+
RO32(0xC99, hpmcounter25h)
103+
RO32(0xC9A, hpmcounter26h)
104+
RO32(0xC9B, hpmcounter27h)
105+
RO32(0xC9C, hpmcounter28h)
106+
RO32(0xC9D, hpmcounter29h)
107+
RO32(0xC9E, hpmcounter30h)
108+
RO32(0xC9F, hpmcounter31h)
109+
110+
// Supervisor Trap Setup
111+
RW(0x100, sstatus) // Supervisor status register
112+
RW(0x102, sedeleg) // Supervisor exception delegation register
113+
RW(0x103, sideleg) // Supervisor interrupt delegation register
114+
RW(0x104, sie) // Supervisor interrupt-enable register
115+
RW(0x105, stvec) // Supervisor trap handler base address
116+
RW(0x106, scounteren) // Supervisor counter enable
117+
118+
// Supervisor Trap Handling
119+
RW(0x140, sscratch) // Scratch register for supervisor trap handlers
120+
RW(0x141, sepc) // Supervisor exception program counter
121+
RW(0x142, scause) // Supervisor trap cause
122+
RW(0x143, stval) // Supervisor bad address or instruction
123+
RW(0x144, sip) // Supervisor interrupt pending
124+
125+
// Supervisor Protection and Translation
126+
RW(0x180, satp) // Supervisor address translation and protection
127+
128+
// Machine Information Registers
129+
RO(0xF11, mvendorid) // Vendor ID
130+
RO(0xF12, marchid) // Architecture ID
131+
RO(0xF13, mimpid) // Implementation ID
132+
RO(0xF14, mhartid) // Hardware thread ID
133+
134+
// Machine Trap Setup
135+
RW(0x300, mstatus) // Machine status register
136+
RW(0x301, misa) // ISA and extensions
137+
RW(0x302, medeleg) // Machine exception delegation register
138+
RW(0x303, mideleg) // Machine interrupt delegation register
139+
RW(0x304, mie) // Machine interrupt-enable register
140+
RW(0x305, mtvec) // Machine trap handler base address
141+
RW(0x306, mcounteren) // Machine counter enable
142+
143+
// Machine Trap Handling
144+
RW(0x340, mscratch) // Scratch register for machine trap handlers
145+
RW(0x341, mepc) // Machine exception program counter
146+
RW(0x342, mcause) // Machine trap cause
147+
RW(0x343, mtval) // Machine bad address or instruction
148+
RW(0x344, mip) // Machine interrupt pending
149+
150+
// Machine Protection and Translation
151+
RW( 0x3A0, pmpcfg0) // Physical memory protection configuration
152+
RW32(0x3A1, pmpcfg1) // Physical memory protection configuration, RV32 only
153+
RW( 0x3A2, pmpcfg2) // Physical memory protection configuration
154+
RW32(0x3A3, pmpcfg3) // Physical memory protection configuration, RV32 only
155+
RW( 0x3B0, pmpaddr0) // Physical memory protection address register
156+
RW( 0x3B1, pmpaddr1) // Physical memory protection address register
157+
RW( 0x3B2, pmpaddr2) // Physical memory protection address register
158+
RW( 0x3B3, pmpaddr3) // Physical memory protection address register
159+
RW( 0x3B4, pmpaddr4) // Physical memory protection address register
160+
RW( 0x3B5, pmpaddr5) // Physical memory protection address register
161+
RW( 0x3B6, pmpaddr6) // Physical memory protection address register
162+
RW( 0x3B7, pmpaddr7) // Physical memory protection address register
163+
RW( 0x3B8, pmpaddr8) // Physical memory protection address register
164+
RW( 0x3B9, pmpaddr9) // Physical memory protection address register
165+
RW( 0x3BA, pmpaddr10) // Physical memory protection address register
166+
RW( 0x3BB, pmpaddr11) // Physical memory protection address register
167+
RW( 0x3BC, pmpaddr12) // Physical memory protection address register
168+
RW( 0x3BD, pmpaddr13) // Physical memory protection address register
169+
RW( 0x3BE, pmpaddr14) // Physical memory protection address register
170+
RW( 0x3BF, pmpaddr15) // Physical memory protection address register
171+
172+
// Machine Counter/Timers
173+
RO( 0xB00, mcycle) // Machine cycle counter
174+
RO( 0xB02, minstret) // Machine instructions-retired counter
175+
RO( 0xB03, mhpmcounter3) // Machine performance-monitoring counter
176+
RO( 0xB04, mhpmcounter4) // Machine performance-monitoring counter
177+
RO( 0xB05, mhpmcounter5) // Machine performance-monitoring counter
178+
RO( 0xB06, mhpmcounter6) // Machine performance-monitoring counter
179+
RO( 0xB07, mhpmcounter7) // Machine performance-monitoring counter
180+
RO( 0xB08, mhpmcounter8) // Machine performance-monitoring counter
181+
RO( 0xB09, mhpmcounter9) // Machine performance-monitoring counter
182+
RO( 0xB0A, mhpmcounter10) // Machine performance-monitoring counter
183+
RO( 0xB0B, mhpmcounter11) // Machine performance-monitoring counter
184+
RO( 0xB0C, mhpmcounter12) // Machine performance-monitoring counter
185+
RO( 0xB0D, mhpmcounter13) // Machine performance-monitoring counter
186+
RO( 0xB0E, mhpmcounter14) // Machine performance-monitoring counter
187+
RO( 0xB0F, mhpmcounter15) // Machine performance-monitoring counter
188+
RO( 0xB10, mhpmcounter16) // Machine performance-monitoring counter
189+
RO( 0xB11, mhpmcounter17) // Machine performance-monitoring counter
190+
RO( 0xB12, mhpmcounter18) // Machine performance-monitoring counter
191+
RO( 0xB13, mhpmcounter19) // Machine performance-monitoring counter
192+
RO( 0xB14, mhpmcounter20) // Machine performance-monitoring counter
193+
RO( 0xB15, mhpmcounter21) // Machine performance-monitoring counter
194+
RO( 0xB16, mhpmcounter22) // Machine performance-monitoring counter
195+
RO( 0xB17, mhpmcounter23) // Machine performance-monitoring counter
196+
RO( 0xB18, mhpmcounter24) // Machine performance-monitoring counter
197+
RO( 0xB19, mhpmcounter25) // Machine performance-monitoring counter
198+
RO( 0xB1A, mhpmcounter26) // Machine performance-monitoring counter
199+
RO( 0xB1B, mhpmcounter27) // Machine performance-monitoring counter
200+
RO( 0xB1C, mhpmcounter28) // Machine performance-monitoring counter
201+
RO( 0xB1D, mhpmcounter29) // Machine performance-monitoring counter
202+
RO( 0xB1E, mhpmcounter30) // Machine performance-monitoring counter
203+
RO( 0xB1F, mhpmcounter31) // Machine performance-monitoring counter
204+
RO32(0xB80, mcycleh) // Upper 32 bits of mcycle, RV32I only
205+
RO32(0xB82, minstreth) // Upper 32 bits of minstret, RV32I only
206+
RO32(0xB83, mhpmcounter3h) // Upper 32 bits of mhpmcounter3, RV32I only
207+
RO32(0xB84, mhpmcounter4h)
208+
RO32(0xB85, mhpmcounter5h)
209+
RO32(0xB86, mhpmcounter6h)
210+
RO32(0xB87, mhpmcounter7h)
211+
RO32(0xB88, mhpmcounter8h)
212+
RO32(0xB89, mhpmcounter9h)
213+
RO32(0xB8A, mhpmcounter10h)
214+
RO32(0xB8B, mhpmcounter11h)
215+
RO32(0xB8C, mhpmcounter12h)
216+
RO32(0xB8D, mhpmcounter13h)
217+
RO32(0xB8E, mhpmcounter14h)
218+
RO32(0xB8F, mhpmcounter15h)
219+
RO32(0xB90, mhpmcounter16h)
220+
RO32(0xB91, mhpmcounter17h)
221+
RO32(0xB92, mhpmcounter18h)
222+
RO32(0xB93, mhpmcounter19h)
223+
RO32(0xB94, mhpmcounter20h)
224+
RO32(0xB95, mhpmcounter21h)
225+
RO32(0xB96, mhpmcounter22h)
226+
RO32(0xB97, mhpmcounter23h)
227+
RO32(0xB98, mhpmcounter24h)
228+
RO32(0xB99, mhpmcounter25h)
229+
RO32(0xB9A, mhpmcounter26h)
230+
RO32(0xB9B, mhpmcounter27h)
231+
RO32(0xB9C, mhpmcounter28h)
232+
RO32(0xB9D, mhpmcounter29h)
233+
RO32(0xB9E, mhpmcounter30h)
234+
RO32(0xB9F, mhpmcounter31h)
235+
236+
RW(0x323, mhpmevent3) // Machine performance-monitoring event selector
237+
RW(0x324, mhpmevent4) // Machine performance-monitoring event selector
238+
RW(0x325, mhpmevent5) // Machine performance-monitoring event selector
239+
RW(0x326, mhpmevent6) // Machine performance-monitoring event selector
240+
RW(0x327, mhpmevent7) // Machine performance-monitoring event selector
241+
RW(0x328, mhpmevent8) // Machine performance-monitoring event selector
242+
RW(0x329, mhpmevent9) // Machine performance-monitoring event selector
243+
RW(0x32A, mhpmevent10) // Machine performance-monitoring event selector
244+
RW(0x32B, mhpmevent11) // Machine performance-monitoring event selector
245+
RW(0x32C, mhpmevent12) // Machine performance-monitoring event selector
246+
RW(0x32D, mhpmevent13) // Machine performance-monitoring event selector
247+
RW(0x32E, mhpmevent14) // Machine performance-monitoring event selector
248+
RW(0x32F, mhpmevent15) // Machine performance-monitoring event selector
249+
RW(0x330, mhpmevent16) // Machine performance-monitoring event selector
250+
RW(0x331, mhpmevent17) // Machine performance-monitoring event selector
251+
RW(0x332, mhpmevent18) // Machine performance-monitoring event selector
252+
RW(0x333, mhpmevent19) // Machine performance-monitoring event selector
253+
RW(0x334, mhpmevent20) // Machine performance-monitoring event selector
254+
RW(0x335, mhpmevent21) // Machine performance-monitoring event selector
255+
RW(0x336, mhpmevent22) // Machine performance-monitoring event selector
256+
RW(0x337, mhpmevent23) // Machine performance-monitoring event selector
257+
RW(0x338, mhpmevent24) // Machine performance-monitoring event selector
258+
RW(0x339, mhpmevent25) // Machine performance-monitoring event selector
259+
RW(0x33A, mhpmevent26) // Machine performance-monitoring event selector
260+
RW(0x33B, mhpmevent27) // Machine performance-monitoring event selector
261+
RW(0x33C, mhpmevent28) // Machine performance-monitoring event selector
262+
RW(0x33D, mhpmevent29) // Machine performance-monitoring event selector
263+
RW(0x33E, mhpmevent30) // Machine performance-monitoring event selector
264+
RW(0x33F, mhpmevent31) // Machine performance-monitoring event selector
265+
266+
// Debug/Trace Registers (shared with Debug Mode)
267+
RW(0x7A0, tselect) // Debug/Trace trigger register select
268+
RW(0x7A1, tdata1) // First Debug/Trace trigger data register
269+
RW(0x7A2, tdata2) // Second Debug/Trace trigger data register
270+
RW(0x7A3, tdata3) // Third Debug/Trace trigger data register
271+
272+
// Debug Mode Registers
273+
RW(0x7B0, dcsr) // Debug control and status register
274+
RW(0x7B1, dpc) // Debug PC
275+
RW(0x7B2, dscratch) // Debug scratch register

‎asm.h

+11
Original file line numberDiff line numberDiff line change
@@ -33,5 +33,16 @@ __clear_ ## name: \
3333
#define REG_READ_WRITE(name, offset) REG_READ(name, offset); REG_WRITE(name, offset)
3434
#define REG_SET_CLEAR(name, offset) REG_SET(name, offset); REG_CLEAR(name, offset)
3535

36+
#define RW(offset, name) REG_READ_WRITE(name, offset); REG_SET_CLEAR(name, offset)
37+
#define RO(offset, name) REG_READ(name, offset)
38+
39+
#if __riscv_xlen == 32
40+
#define RW32(offset, name) RW(offset, name)
41+
#define RO32(offset, name) RO(offset, name)
42+
#else
43+
#define RW32(offset, name)
44+
#define RO32(offset, name)
45+
#endif
46+
3647
#endif /* __ASM_H */
3748

‎asm32.S

-5
This file was deleted.

‎assemble.sh

+3-5
Original file line numberDiff line numberDiff line change
@@ -7,14 +7,12 @@ crate=riscv
77
# remove existing blobs because otherwise this will append object files to the old blobs
88
rm -f bin/*.a
99

10-
riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm.S -o bin/$crate.o
11-
riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imac asm32.S -o bin/$crate-32.o
12-
ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o bin/$crate-32.o
13-
ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o bin/$crate-32.o
10+
riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imc asm.S -o bin/$crate.o
11+
ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
12+
ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
1413

1514
riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
1615
ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
1716
ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
1817

1918
rm bin/$crate.o
20-
rm bin/$crate-32.o

‎bin/riscv32imac-unknown-none-elf.a

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‎bin/riscv32imc-unknown-none-elf.a

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‎bin/riscv64gc-unknown-none-elf.a

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‎bin/riscv64imac-unknown-none-elf.a

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‎src/register/fcsr.rs

+1
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,7 @@ impl Flags {
6464
}
6565

6666
/// Rounding Mode
67+
#[derive(Clone, Copy, Debug, Eq, PartialEq)]
6768
pub enum RoundingMode {
6869
RoundToNearestEven = 0b000,
6970
RoundTowardsZero = 0b001,

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