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Auto merge of #51953 - japaric:atomic-load-store, r=alexcrichton
enable Atomic*.{load,store} for ARMv6-M / MSP430 closes #45085 as proposed in #45085 (comment) this commit adds an `atomic_cas` target option and extends the `#[cfg(target_has_atomic)]` attribute to enable a subset of the `Atomic*` API on architectures that don't support atomic CAS natively, like MSP430 and ARMv6-M. r? @alexcrichton
2 parents 4d9fa23 + f9145d0 commit 0072c95

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9 files changed

+52
-13
lines changed

9 files changed

+52
-13
lines changed

src/liballoc/lib.rs

+4-1
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,10 @@ mod boxed {
162162
#[cfg(test)]
163163
mod boxed_test;
164164
pub mod collections;
165-
#[cfg(target_has_atomic = "ptr")]
165+
#[cfg(any(
166+
all(stage0, target_has_atomic = "ptr"),
167+
all(not(stage0), target_has_atomic = "ptr", target_has_atomic = "cas")
168+
))]
166169
pub mod sync;
167170
pub mod rc;
168171
pub mod raw_vec;

src/liballoc/task.rs

+12-3
Original file line numberDiff line numberDiff line change
@@ -12,10 +12,16 @@
1212
1313
pub use core::task::*;
1414

15-
#[cfg(target_has_atomic = "ptr")]
15+
#[cfg(any(
16+
all(stage0, target_has_atomic = "ptr"),
17+
all(not(stage0), target_has_atomic = "ptr", target_has_atomic = "cas")
18+
))]
1619
pub use self::if_arc::*;
1720

18-
#[cfg(target_has_atomic = "ptr")]
21+
#[cfg(any(
22+
all(stage0, target_has_atomic = "ptr"),
23+
all(not(stage0), target_has_atomic = "ptr", target_has_atomic = "cas")
24+
))]
1925
mod if_arc {
2026
use super::*;
2127
use core::marker::PhantomData;
@@ -47,7 +53,10 @@ mod if_arc {
4753
}
4854
}
4955

50-
#[cfg(target_has_atomic = "ptr")]
56+
#[cfg(any(
57+
all(stage0, target_has_atomic = "ptr"),
58+
all(not(stage0), target_has_atomic = "ptr", target_has_atomic = "cas")
59+
))]
5160
struct ArcWrapped<T>(PhantomData<T>);
5261

5362
unsafe impl<T: Wake + 'static> UnsafeWake for ArcWrapped<T> {

src/libcore/sync/atomic.rs

+16
Original file line numberDiff line numberDiff line change
@@ -371,6 +371,7 @@ impl AtomicBool {
371371
/// ```
372372
#[inline]
373373
#[stable(feature = "rust1", since = "1.0.0")]
374+
#[cfg(any(stage0, target_has_atomic = "cas"))]
374375
pub fn swap(&self, val: bool, order: Ordering) -> bool {
375376
unsafe { atomic_swap(self.v.get(), val as u8, order) != 0 }
376377
}
@@ -401,6 +402,7 @@ impl AtomicBool {
401402
/// ```
402403
#[inline]
403404
#[stable(feature = "rust1", since = "1.0.0")]
405+
#[cfg(any(stage0, target_has_atomic = "cas"))]
404406
pub fn compare_and_swap(&self, current: bool, new: bool, order: Ordering) -> bool {
405407
match self.compare_exchange(current, new, order, strongest_failure_ordering(order)) {
406408
Ok(x) => x,
@@ -446,6 +448,7 @@ impl AtomicBool {
446448
/// ```
447449
#[inline]
448450
#[stable(feature = "extended_compare_and_swap", since = "1.10.0")]
451+
#[cfg(any(stage0, target_has_atomic = "cas"))]
449452
pub fn compare_exchange(&self,
450453
current: bool,
451454
new: bool,
@@ -537,6 +540,7 @@ impl AtomicBool {
537540
/// ```
538541
#[inline]
539542
#[stable(feature = "rust1", since = "1.0.0")]
543+
#[cfg(any(stage0, target_has_atomic = "cas"))]
540544
pub fn fetch_and(&self, val: bool, order: Ordering) -> bool {
541545
unsafe { atomic_and(self.v.get(), val as u8, order) != 0 }
542546
}
@@ -568,6 +572,7 @@ impl AtomicBool {
568572
/// ```
569573
#[inline]
570574
#[stable(feature = "rust1", since = "1.0.0")]
575+
#[cfg(any(stage0, target_has_atomic = "cas"))]
571576
pub fn fetch_nand(&self, val: bool, order: Ordering) -> bool {
572577
// We can't use atomic_nand here because it can result in a bool with
573578
// an invalid value. This happens because the atomic operation is done
@@ -610,6 +615,7 @@ impl AtomicBool {
610615
/// ```
611616
#[inline]
612617
#[stable(feature = "rust1", since = "1.0.0")]
618+
#[cfg(any(stage0, target_has_atomic = "cas"))]
613619
pub fn fetch_or(&self, val: bool, order: Ordering) -> bool {
614620
unsafe { atomic_or(self.v.get(), val as u8, order) != 0 }
615621
}
@@ -640,6 +646,7 @@ impl AtomicBool {
640646
/// ```
641647
#[inline]
642648
#[stable(feature = "rust1", since = "1.0.0")]
649+
#[cfg(any(stage0, target_has_atomic = "cas"))]
643650
pub fn fetch_xor(&self, val: bool, order: Ordering) -> bool {
644651
unsafe { atomic_xor(self.v.get(), val as u8, order) != 0 }
645652
}
@@ -786,6 +793,7 @@ impl<T> AtomicPtr<T> {
786793
/// ```
787794
#[inline]
788795
#[stable(feature = "rust1", since = "1.0.0")]
796+
#[cfg(any(stage0, target_has_atomic = "cas"))]
789797
pub fn swap(&self, ptr: *mut T, order: Ordering) -> *mut T {
790798
unsafe { atomic_swap(self.p.get() as *mut usize, ptr as usize, order) as *mut T }
791799
}
@@ -815,6 +823,7 @@ impl<T> AtomicPtr<T> {
815823
/// ```
816824
#[inline]
817825
#[stable(feature = "rust1", since = "1.0.0")]
826+
#[cfg(any(stage0, target_has_atomic = "cas"))]
818827
pub fn compare_and_swap(&self, current: *mut T, new: *mut T, order: Ordering) -> *mut T {
819828
match self.compare_exchange(current, new, order, strongest_failure_ordering(order)) {
820829
Ok(x) => x,
@@ -853,6 +862,7 @@ impl<T> AtomicPtr<T> {
853862
/// ```
854863
#[inline]
855864
#[stable(feature = "extended_compare_and_swap", since = "1.10.0")]
865+
#[cfg(any(stage0, target_has_atomic = "cas"))]
856866
pub fn compare_exchange(&self,
857867
current: *mut T,
858868
new: *mut T,
@@ -1138,6 +1148,7 @@ assert_eq!(some_var.swap(10, Ordering::Relaxed), 5);
11381148
```"),
11391149
#[inline]
11401150
#[$stable]
1151+
#[cfg(any(stage0, target_has_atomic = "cas"))]
11411152
pub fn swap(&self, val: $int_type, order: Ordering) -> $int_type {
11421153
unsafe { atomic_swap(self.v.get(), val, order) }
11431154
}
@@ -1170,6 +1181,7 @@ assert_eq!(some_var.load(Ordering::Relaxed), 10);
11701181
```"),
11711182
#[inline]
11721183
#[$stable]
1184+
#[cfg(any(stage0, target_has_atomic = "cas"))]
11731185
pub fn compare_and_swap(&self,
11741186
current: $int_type,
11751187
new: $int_type,
@@ -1223,6 +1235,7 @@ assert_eq!(some_var.load(Ordering::Relaxed), 10);
12231235
```"),
12241236
#[inline]
12251237
#[$stable_cxchg]
1238+
#[cfg(any(stage0, target_has_atomic = "cas"))]
12261239
pub fn compare_exchange(&self,
12271240
current: $int_type,
12281241
new: $int_type,
@@ -1677,6 +1690,7 @@ atomic_int!{
16771690
}
16781691

16791692
#[inline]
1693+
#[cfg(any(stage0, target_has_atomic = "cas"))]
16801694
fn strongest_failure_ordering(order: Ordering) -> Ordering {
16811695
match order {
16821696
Release => Relaxed,
@@ -1713,6 +1727,7 @@ unsafe fn atomic_load<T>(dst: *const T, order: Ordering) -> T {
17131727
}
17141728

17151729
#[inline]
1730+
#[cfg(any(stage0, target_has_atomic = "cas"))]
17161731
unsafe fn atomic_swap<T>(dst: *mut T, val: T, order: Ordering) -> T {
17171732
match order {
17181733
Acquire => intrinsics::atomic_xchg_acq(dst, val),
@@ -1751,6 +1766,7 @@ unsafe fn atomic_sub<T>(dst: *mut T, val: T, order: Ordering) -> T {
17511766
}
17521767

17531768
#[inline]
1769+
#[cfg(any(stage0, target_has_atomic = "cas"))]
17541770
unsafe fn atomic_compare_exchange<T>(dst: *mut T,
17551771
old: T,
17561772
new: T,

src/librustc/session/config.rs

+4
Original file line numberDiff line numberDiff line change
@@ -1369,6 +1369,7 @@ pub fn default_configuration(sess: &Session) -> ast::CrateConfig {
13691369
let vendor = &sess.target.target.target_vendor;
13701370
let min_atomic_width = sess.target.target.min_atomic_width();
13711371
let max_atomic_width = sess.target.target.max_atomic_width();
1372+
let atomic_cas = sess.target.target.options.atomic_cas;
13721373

13731374
let mut ret = HashSet::new();
13741375
// Target bindings.
@@ -1408,6 +1409,9 @@ pub fn default_configuration(sess: &Session) -> ast::CrateConfig {
14081409
}
14091410
}
14101411
}
1412+
if atomic_cas {
1413+
ret.insert((Symbol::intern("target_has_atomic"), Some(Symbol::intern("cas"))));
1414+
}
14111415
if sess.opts.debug_assertions {
14121416
ret.insert((Symbol::intern("debug_assertions"), None));
14131417
}

src/librustc_target/spec/mod.rs

+6
Original file line numberDiff line numberDiff line change
@@ -573,6 +573,9 @@ pub struct TargetOptions {
573573
/// Don't use this field; instead use the `.max_atomic_width()` method.
574574
pub max_atomic_width: Option<u64>,
575575

576+
/// Whether the target supports atomic CAS operations natively
577+
pub atomic_cas: bool,
578+
576579
/// Panic strategy: "unwind" or "abort"
577580
pub panic_strategy: PanicStrategy,
578581

@@ -691,6 +694,7 @@ impl Default for TargetOptions {
691694
no_integrated_as: false,
692695
min_atomic_width: None,
693696
max_atomic_width: None,
697+
atomic_cas: true,
694698
panic_strategy: PanicStrategy::Unwind,
695699
abi_blacklist: vec![],
696700
crt_static_allows_dylibs: false,
@@ -947,6 +951,7 @@ impl Target {
947951
key!(no_integrated_as, bool);
948952
key!(max_atomic_width, Option<u64>);
949953
key!(min_atomic_width, Option<u64>);
954+
key!(atomic_cas, bool);
950955
try!(key!(panic_strategy, PanicStrategy));
951956
key!(crt_static_allows_dylibs, bool);
952957
key!(crt_static_default, bool);
@@ -1155,6 +1160,7 @@ impl ToJson for Target {
11551160
target_option_val!(no_integrated_as);
11561161
target_option_val!(min_atomic_width);
11571162
target_option_val!(max_atomic_width);
1163+
target_option_val!(atomic_cas);
11581164
target_option_val!(panic_strategy);
11591165
target_option_val!(crt_static_allows_dylibs);
11601166
target_option_val!(crt_static_default);

src/librustc_target/spec/msp430_none_elf.rs

+3-2
Original file line numberDiff line numberDiff line change
@@ -34,9 +34,10 @@ pub fn target() -> TargetResult {
3434
linker: Some("msp430-elf-gcc".to_string()),
3535
no_integrated_as: true,
3636

37-
// There are no atomic instructions available in the MSP430
37+
// There are no atomic CAS instructions available in the MSP430
3838
// instruction set
39-
max_atomic_width: Some(0),
39+
max_atomic_width: Some(16),
40+
atomic_cas: false,
4041

4142
// Because these devices have very little resources having an
4243
// unwinder is too onerous so we default to "abort" because the

src/librustc_target/spec/thumbv6m_none_eabi.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -29,9 +29,9 @@ pub fn target() -> TargetResult {
2929
// The ARMv6-M architecture doesn't support unaligned loads/stores so we disable them
3030
// with +strict-align.
3131
features: "+strict-align".to_string(),
32-
// There are no atomic instructions available in the instruction set of the ARMv6-M
32+
// There are no atomic CAS instructions available in the instruction set of the ARMv6-M
3333
// architecture
34-
max_atomic_width: Some(0),
34+
atomic_cas: false,
3535
.. super::thumb_base::opts()
3636
}
3737
})
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
-include ../tools.mk
2+
3+
# The target used below doesn't support atomic CAS operations. Verify that's the case
4+
all:
5+
$(RUSTC) --print cfg --target thumbv6m-none-eabi | $(CGREP) -v 'target_has_atomic="cas"'

src/test/run-make-fulldeps/target-without-atomics/Makefile

-5
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