From e0cdbe6b3cb1af8f038e4ac93c1d59280cb1db56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 21:14:27 +0100 Subject: [PATCH 01/73] convert `_mm_aeskeygenassist_si128` to const generics --- crates/core_arch/src/x86/aes.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/aes.rs b/crates/core_arch/src/x86/aes.rs index 603744aef6..ffded1a0dc 100644 --- a/crates/core_arch/src/x86/aes.rs +++ b/crates/core_arch/src/x86/aes.rs @@ -87,21 +87,17 @@ pub unsafe fn _mm_aesimc_si128(a: __m128i) -> __m128i { /// /// Assist in expanding the AES cipher key by computing steps towards /// generating a round key for encryption cipher using data from `a` and an -/// 8-bit round constant `imm8`. +/// 8-bit round constant `IMM8`. /// /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_aeskeygenassist_si128) #[inline] #[target_feature(enable = "aes")] -#[cfg_attr(test, assert_instr(aeskeygenassist, imm8 = 0))] -#[rustc_args_required_const(1)] +#[cfg_attr(test, assert_instr(aeskeygenassist, IMM8 = 0))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] -pub unsafe fn _mm_aeskeygenassist_si128(a: __m128i, imm8: i32) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - aeskeygenassist(a, $imm8) - }; - } - constify_imm8!(imm8, call) +pub unsafe fn _mm_aeskeygenassist_si128(a: __m128i) -> __m128i { + static_assert_imm8!(IMM8); + aeskeygenassist(a, IMM8 as u8) } #[cfg(test)] @@ -169,7 +165,7 @@ mod tests { // Constants taken from https://msdn.microsoft.com/en-us/library/cc714138.aspx. let a = _mm_set_epi64x(0x0123456789abcdef, 0x8899aabbccddeeff); let e = _mm_set_epi64x(0x857c266b7c266e85, 0xeac4eea9c4eeacea); - let r = _mm_aeskeygenassist_si128(a, 5); + let r = _mm_aeskeygenassist_si128::<5>(a); assert_eq_m128i(r, e); } } From 5d60cb4184f1a070eed312e89211602b36c3115f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 21:15:31 +0100 Subject: [PATCH 02/73] convert `_mm_extract_epi64` to const generics --- crates/core_arch/src/x86_64/sse41.rs | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/crates/core_arch/src/x86_64/sse41.rs b/crates/core_arch/src/x86_64/sse41.rs index 1b37967325..d0fd68d5f5 100644 --- a/crates/core_arch/src/x86_64/sse41.rs +++ b/crates/core_arch/src/x86_64/sse41.rs @@ -8,20 +8,17 @@ use crate::{ #[cfg(test)] use stdarch_test::assert_instr; -/// Extracts an 64-bit integer from `a` selected with `imm8` +/// Extracts an 64-bit integer from `a` selected with `IMM1` /// /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_extract_epi64) #[inline] #[target_feature(enable = "sse4.1")] -#[cfg_attr(all(test, not(target_os = "windows")), assert_instr(pextrq, imm8 = 1))] -#[rustc_args_required_const(1)] +#[cfg_attr(all(test, not(target_os = "windows")), assert_instr(pextrq, IMM1 = 1))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] -pub unsafe fn _mm_extract_epi64(a: __m128i, imm8: i32) -> i64 { - let a = a.as_i64x2(); - match imm8 & 1 { - 0 => simd_extract(a, 0), - _ => simd_extract(a, 1), - } +pub unsafe fn _mm_extract_epi64(a: __m128i) -> i64 { + static_assert_imm1!(IMM1); + simd_extract(a.as_i64x2(), IMM1 as u32) } /// Returns a copy of `a` with the 64-bit integer from `i` inserted at a @@ -49,10 +46,10 @@ mod tests { #[simd_test(enable = "sse4.1")] unsafe fn test_mm_extract_epi64() { let a = _mm_setr_epi64x(0, 1); - let r = _mm_extract_epi64(a, 1); - assert_eq!(r, 1); - let r = _mm_extract_epi64(a, 3); + let r = _mm_extract_epi64::<1>(a); assert_eq!(r, 1); + let r = _mm_extract_epi64::<0>(a); + assert_eq!(r, 0); } #[simd_test(enable = "sse4.1")] From d538c7eb4572d6ec4d78e84f291d32d7cd18fdae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 21:15:59 +0100 Subject: [PATCH 03/73] convert `_mm_insert_epi64` to const generics --- crates/core_arch/src/x86/avx2.rs | 2 +- crates/core_arch/src/x86/test.rs | 6 ++++-- crates/core_arch/src/x86_64/sse41.rs | 20 +++++++++----------- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/crates/core_arch/src/x86/avx2.rs b/crates/core_arch/src/x86/avx2.rs index b6952d03a1..138f7ce292 100644 --- a/crates/core_arch/src/x86/avx2.rs +++ b/crates/core_arch/src/x86/avx2.rs @@ -5184,7 +5184,7 @@ mod tests { #[simd_test(enable = "avx2")] unsafe fn test_mm256_sll_epi64() { let a = _mm256_set1_epi64x(0xFFFFFFFF); - let b = _mm_insert_epi64(_mm_set1_epi64x(0), 4, 0); + let b = _mm_insert_epi64::<0>(_mm_set1_epi64x(0), 4); let r = _mm256_sll_epi64(a, b); assert_eq_m256i(r, _mm256_set1_epi64x(0xFFFFFFFF0)); } diff --git a/crates/core_arch/src/x86/test.rs b/crates/core_arch/src/x86/test.rs index 9f577972fa..9f8b969301 100644 --- a/crates/core_arch/src/x86/test.rs +++ b/crates/core_arch/src/x86/test.rs @@ -92,14 +92,16 @@ pub unsafe fn get_m512i(a: __m512i, idx: usize) -> i64 { mod x86_polyfill { use crate::core_arch::x86::*; - pub unsafe fn _mm_insert_epi64(a: __m128i, val: i64, idx: i32) -> __m128i { + #[rustc_legacy_const_generics(2)] + pub unsafe fn _mm_insert_epi64(a: __m128i, val: i64) -> __m128i { + static_assert_imm1!(INDEX); #[repr(C)] union A { a: __m128i, b: [i64; 2], } let mut a = A { a }; - a.b[idx as usize] = val; + a.b[INDEX as usize] = val; a.a } diff --git a/crates/core_arch/src/x86_64/sse41.rs b/crates/core_arch/src/x86_64/sse41.rs index d0fd68d5f5..3d1ea0cf65 100644 --- a/crates/core_arch/src/x86_64/sse41.rs +++ b/crates/core_arch/src/x86_64/sse41.rs @@ -22,20 +22,17 @@ pub unsafe fn _mm_extract_epi64(a: __m128i) -> i64 { } /// Returns a copy of `a` with the 64-bit integer from `i` inserted at a -/// location specified by `imm8`. +/// location specified by `IMM1`. /// /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_insert_epi64) #[inline] #[target_feature(enable = "sse4.1")] -#[cfg_attr(test, assert_instr(pinsrq, imm8 = 0))] -#[rustc_args_required_const(2)] +#[cfg_attr(test, assert_instr(pinsrq, IMM1 = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "simd_x86", since = "1.27.0")] -pub unsafe fn _mm_insert_epi64(a: __m128i, i: i64, imm8: i32) -> __m128i { - let a = a.as_i64x2(); - match imm8 & 1 { - 0 => transmute(simd_insert(a, 0, i)), - _ => transmute(simd_insert(a, 1, i)), - } +pub unsafe fn _mm_insert_epi64(a: __m128i, i: i64) -> __m128i { + static_assert_imm1!(IMM1); + transmute(simd_insert(a.as_i64x2(), IMM1 as u32, i)) } #[cfg(test)] @@ -56,9 +53,10 @@ mod tests { unsafe fn test_mm_insert_epi64() { let a = _mm_set1_epi64x(0); let e = _mm_setr_epi64x(0, 32); - let r = _mm_insert_epi64(a, 32, 1); + let r = _mm_insert_epi64::<1>(a, 32); assert_eq_m128i(r, e); - let r = _mm_insert_epi64(a, 32, 3); + let e = _mm_setr_epi64x(32, 0); + let r = _mm_insert_epi64::<0>(a, 32); assert_eq_m128i(r, e); } } From 2ab199f6bb65bd25b13796912e71edfae5806bdb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 21:25:17 +0100 Subject: [PATCH 04/73] convert `_mm256_extract_epi64` to const generics --- crates/core_arch/src/x86_64/avx2.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86_64/avx2.rs b/crates/core_arch/src/x86_64/avx2.rs index 0f81cd221f..14447a1371 100644 --- a/crates/core_arch/src/x86_64/avx2.rs +++ b/crates/core_arch/src/x86_64/avx2.rs @@ -20,22 +20,17 @@ use crate::core_arch::{simd_llvm::*, x86::*}; -/// Extracts a 64-bit integer from `a`, selected with `imm8`. +/// Extracts a 64-bit integer from `a`, selected with `INDEX`. /// /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extract_epi64) #[inline] #[target_feature(enable = "avx2")] -#[rustc_args_required_const(1)] +#[rustc_legacy_const_generics(1)] // This intrinsic has no corresponding instruction. #[stable(feature = "simd_x86", since = "1.27.0")] -pub unsafe fn _mm256_extract_epi64(a: __m256i, imm8: i32) -> i64 { - let a = a.as_i64x4(); - match imm8 & 3 { - 0 => simd_extract(a, 0), - 1 => simd_extract(a, 1), - 2 => simd_extract(a, 2), - _ => simd_extract(a, 3), - } +pub unsafe fn _mm256_extract_epi64(a: __m256i) -> i64 { + static_assert_imm2!(INDEX); + simd_extract(a.as_i64x4(), INDEX as u32) } #[cfg(test)] @@ -46,7 +41,7 @@ mod tests { #[simd_test(enable = "avx2")] unsafe fn test_mm256_extract_epi64() { let a = _mm256_setr_epi64x(0, 1, 2, 3); - let r = _mm256_extract_epi64(a, 3); + let r = _mm256_extract_epi64::<3>(a); assert_eq!(r, 3); } } From 5391f5e109ddd22b306ce83eae79258230020ef6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 21:31:46 +0100 Subject: [PATCH 05/73] convert `_mm_sha1rnds4_epu32` to const generics --- crates/core_arch/src/x86/sha.rs | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/crates/core_arch/src/x86/sha.rs b/crates/core_arch/src/x86/sha.rs index 362a97ccd3..cfb330cfbb 100644 --- a/crates/core_arch/src/x86/sha.rs +++ b/crates/core_arch/src/x86/sha.rs @@ -66,25 +66,18 @@ pub unsafe fn _mm_sha1nexte_epu32(a: __m128i, b: __m128i) -> __m128i { /// Performs four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D) /// from `a` and some pre-computed sum of the next 4 round message values /// (unsigned 32-bit integers), and state variable E from `b`, and return the -/// updated SHA1 state (A,B,C,D). `func` contains the logic functions and round +/// updated SHA1 state (A,B,C,D). `FUNC` contains the logic functions and round /// constants. /// /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sha1rnds4_epu32) #[inline] #[target_feature(enable = "sha")] -#[cfg_attr(test, assert_instr(sha1rnds4, func = 0))] -#[rustc_args_required_const(2)] +#[cfg_attr(test, assert_instr(sha1rnds4, FUNC = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "simd_x86", since = "1.27.0")] -pub unsafe fn _mm_sha1rnds4_epu32(a: __m128i, b: __m128i, func: i32) -> __m128i { - let a = a.as_i32x4(); - let b = b.as_i32x4(); - macro_rules! call { - ($imm2:expr) => { - sha1rnds4(a, b, $imm2) - }; - } - let ret = constify_imm2!(func, call); - transmute(ret) +pub unsafe fn _mm_sha1rnds4_epu32(a: __m128i, b: __m128i) -> __m128i { + static_assert_imm2!(FUNC); + transmute(sha1rnds4(a.as_i32x4(), b.as_i32x4(), FUNC as i8)) } /// Performs an intermediate calculation for the next four SHA256 message values @@ -179,19 +172,19 @@ mod tests { let a = _mm_set_epi64x(0xe9b5dba5b5c0fbcf, 0x71374491428a2f98); let b = _mm_set_epi64x(0xab1c5ed5923f82a4, 0x59f111f13956c25b); let expected = _mm_set_epi64x(0x32b13cd8322f5268, 0xc54420862bd9246f); - let r = _mm_sha1rnds4_epu32(a, b, 0); + let r = _mm_sha1rnds4_epu32::<0>(a, b); assert_eq_m128i(r, expected); let expected = _mm_set_epi64x(0x6d4c43e56a3c25d9, 0xa7e00fb775cbd3fe); - let r = _mm_sha1rnds4_epu32(a, b, 1); + let r = _mm_sha1rnds4_epu32::<1>(a, b); assert_eq_m128i(r, expected); let expected = _mm_set_epi64x(0xb304e383c01222f4, 0x66f6b3b1f89d8001); - let r = _mm_sha1rnds4_epu32(a, b, 2); + let r = _mm_sha1rnds4_epu32::<2>(a, b); assert_eq_m128i(r, expected); let expected = _mm_set_epi64x(0x8189b758bfabfa79, 0xdb08f6e78cae098b); - let r = _mm_sha1rnds4_epu32(a, b, 3); + let r = _mm_sha1rnds4_epu32::<3>(a, b); assert_eq_m128i(r, expected); } From e4feec74e1c5b2b1fb9c9ba2dd1762c6467b2205 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 21:32:36 +0100 Subject: [PATCH 06/73] remove unused constify_imm x86 macro --- crates/core_arch/src/x86/macros.rs | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/crates/core_arch/src/x86/macros.rs b/crates/core_arch/src/x86/macros.rs index 4f160221d6..d4c8e363ba 100644 --- a/crates/core_arch/src/x86/macros.rs +++ b/crates/core_arch/src/x86/macros.rs @@ -48,18 +48,6 @@ macro_rules! constify_imm3 { }; } -macro_rules! constify_imm2 { - ($imm8:expr, $expand:ident) => { - #[allow(overflowing_literals)] - match ($imm8) & 0b11 { - 0 => $expand!(0), - 1 => $expand!(1), - 2 => $expand!(2), - _ => $expand!(3), - } - }; -} - // Constifies 5 bits along with an sae option without rounding control. // See: https://github.com/llvm/llvm-project/blob/bd50cf905fa7c0c7caa134301c6ca0658c81eeb1/clang/lib/Sema/SemaChecking.cpp#L3497 #[allow(unused)] From 1b5170878cc36dcd779c87110220114cffc64693 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 21:58:13 +0100 Subject: [PATCH 07/73] convert `_mm_clmulepi64_si128` to const generics --- crates/core_arch/src/x86/avx512vpclmulqdq.rs | 16 +++++----- crates/core_arch/src/x86/pclmulqdq.rs | 32 +++++++++----------- 2 files changed, 22 insertions(+), 26 deletions(-) diff --git a/crates/core_arch/src/x86/avx512vpclmulqdq.rs b/crates/core_arch/src/x86/avx512vpclmulqdq.rs index 831ab7f642..b4e472dc3f 100644 --- a/crates/core_arch/src/x86/avx512vpclmulqdq.rs +++ b/crates/core_arch/src/x86/avx512vpclmulqdq.rs @@ -221,19 +221,19 @@ mod tests { ); verify_512_helper( - |a, b| _mm_clmulepi64_si128(a, b, 0x00), + |a, b| _mm_clmulepi64_si128::<0x00>(a, b), |a, b| _mm512_clmulepi64_epi128(a, b, 0x00), ); verify_512_helper( - |a, b| _mm_clmulepi64_si128(a, b, 0x01), + |a, b| _mm_clmulepi64_si128::<0x01>(a, b), |a, b| _mm512_clmulepi64_epi128(a, b, 0x01), ); verify_512_helper( - |a, b| _mm_clmulepi64_si128(a, b, 0x10), + |a, b| _mm_clmulepi64_si128::<0x10>(a, b), |a, b| _mm512_clmulepi64_epi128(a, b, 0x10), ); verify_512_helper( - |a, b| _mm_clmulepi64_si128(a, b, 0x11), + |a, b| _mm_clmulepi64_si128::<0x11>(a, b), |a, b| _mm512_clmulepi64_epi128(a, b, 0x11), ); } @@ -247,19 +247,19 @@ mod tests { ); verify_256_helper( - |a, b| _mm_clmulepi64_si128(a, b, 0x00), + |a, b| _mm_clmulepi64_si128::<0x00>(a, b), |a, b| _mm256_clmulepi64_epi128(a, b, 0x00), ); verify_256_helper( - |a, b| _mm_clmulepi64_si128(a, b, 0x01), + |a, b| _mm_clmulepi64_si128::<0x01>(a, b), |a, b| _mm256_clmulepi64_epi128(a, b, 0x01), ); verify_256_helper( - |a, b| _mm_clmulepi64_si128(a, b, 0x10), + |a, b| _mm_clmulepi64_si128::<0x10>(a, b), |a, b| _mm256_clmulepi64_epi128(a, b, 0x10), ); verify_256_helper( - |a, b| _mm_clmulepi64_si128(a, b, 0x11), + |a, b| _mm_clmulepi64_si128::<0x11>(a, b), |a, b| _mm256_clmulepi64_epi128(a, b, 0x11), ); } diff --git a/crates/core_arch/src/x86/pclmulqdq.rs b/crates/core_arch/src/x86/pclmulqdq.rs index 0e1bebae9e..6ccf3a62a6 100644 --- a/crates/core_arch/src/x86/pclmulqdq.rs +++ b/crates/core_arch/src/x86/pclmulqdq.rs @@ -25,20 +25,16 @@ extern "C" { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_clmulepi64_si128) #[inline] #[target_feature(enable = "pclmulqdq")] -#[cfg_attr(all(test, not(target_os = "linux")), assert_instr(pclmulqdq, imm8 = 0))] -#[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmullqlqdq, imm8 = 0))] -#[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmulhqlqdq, imm8 = 1))] -#[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmullqhqdq, imm8 = 16))] -#[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmulhqhqdq, imm8 = 17))] -#[rustc_args_required_const(2)] +#[cfg_attr(all(test, not(target_os = "linux")), assert_instr(pclmulqdq, IMM8 = 0))] +#[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmullqlqdq, IMM8 = 0))] +#[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmulhqlqdq, IMM8 = 1))] +#[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmullqhqdq, IMM8 = 16))] +#[cfg_attr(all(test, target_os = "linux"), assert_instr(pclmulhqhqdq, IMM8 = 17))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "simd_x86", since = "1.27.0")] -pub unsafe fn _mm_clmulepi64_si128(a: __m128i, b: __m128i, imm8: i32) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - pclmulqdq(a, b, $imm8) - }; - } - constify_imm8!(imm8, call) +pub unsafe fn _mm_clmulepi64_si128(a: __m128i, b: __m128i) -> __m128i { + static_assert_imm8!(IMM8); + pclmulqdq(a, b, IMM8 as u8) } #[cfg(test)] @@ -62,13 +58,13 @@ mod tests { let r10 = _mm_set_epi64x(0x1a2bf6db3a30862f, 0xbabf262df4b7d5c9); let r11 = _mm_set_epi64x(0x1d1e1f2c592e7c45, 0xd66ee03e410fd4ed); - assert_eq_m128i(_mm_clmulepi64_si128(a, b, 0x00), r00); - assert_eq_m128i(_mm_clmulepi64_si128(a, b, 0x10), r01); - assert_eq_m128i(_mm_clmulepi64_si128(a, b, 0x01), r10); - assert_eq_m128i(_mm_clmulepi64_si128(a, b, 0x11), r11); + assert_eq_m128i(_mm_clmulepi64_si128::<0x00>(a, b), r00); + assert_eq_m128i(_mm_clmulepi64_si128::<0x10>(a, b), r01); + assert_eq_m128i(_mm_clmulepi64_si128::<0x01>(a, b), r10); + assert_eq_m128i(_mm_clmulepi64_si128::<0x11>(a, b), r11); let a0 = _mm_set_epi64x(0x0000000000000000, 0x8000000000000000); let r = _mm_set_epi64x(0x4000000000000000, 0x0000000000000000); - assert_eq_m128i(_mm_clmulepi64_si128(a0, a0, 0x00), r); + assert_eq_m128i(_mm_clmulepi64_si128::<0x00>(a0, a0), r); } } From d42445ff894abb2d17a50897550ef5a262468ee3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:10:08 +0100 Subject: [PATCH 08/73] convert `_mm512_cmp_epu16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index b6fa9d254a..3a7f397292 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3689,22 +3689,18 @@ pub unsafe fn _mm_mask_cmpneq_epi8_mask(k1: __mmask16, a: __m128i, b: __m128i) - _mm_cmpneq_epi8_mask(a, b) & k1 } -/// Compare packed unsigned 16-bit integers in a and b based on the comparison operand specified by imm8, and store the results in mask vector k. +/// Compare packed unsigned 16-bit integers in a and b based on the comparison operand specified by `IMM8`, and store the results in mask vector k. /// /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_epu16_mask&expand=715) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm512_cmp_epu16_mask(a: __m512i, b: __m512i, imm8: i32) -> __mmask32 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm512_cmp_epu16_mask(a: __m512i, b: __m512i) -> __mmask32 { + static_assert_imm3!(IMM8); let a = a.as_u16x32(); let b = b.as_u16x32(); - macro_rules! call { - ($imm3:expr) => { - vpcmpuw(a, b, $imm3, 0b11111111_11111111_11111111_11111111) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpuw(a, b, IMM8, 0b11111111_11111111_11111111_11111111); transmute(r) } @@ -13456,7 +13452,7 @@ mod tests { unsafe fn test_mm512_cmp_epu16_mask() { let a = _mm512_set1_epi16(0); let b = _mm512_set1_epi16(1); - let m = _mm512_cmp_epu16_mask(a, b, _MM_CMPINT_LT); + let m = _mm512_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b); assert_eq!(m, 0b11111111_11111111_11111111_11111111); } From f503771375f01d06e1b426a1e907017551ef121b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:23:55 +0100 Subject: [PATCH 09/73] convert `_mm512_mask_cmp_epu16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 3a7f397292..1feebf50bb 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3709,22 +3709,17 @@ pub unsafe fn _mm512_cmp_epu16_mask(a: __m512i, b: __m512i) -> /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_epu16_mask&expand=716) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm512_mask_cmp_epu16_mask( +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm512_mask_cmp_epu16_mask( k1: __mmask32, a: __m512i, b: __m512i, - imm8: i32, ) -> __mmask32 { + static_assert_imm3!(IMM8); let a = a.as_u16x32(); let b = b.as_u16x32(); - macro_rules! call { - ($imm3:expr) => { - vpcmpuw(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpuw(a, b, IMM8, k1); transmute(r) } @@ -13461,7 +13456,7 @@ mod tests { let a = _mm512_set1_epi16(0); let b = _mm512_set1_epi16(1); let mask = 0b01010101_01010101_01010101_01010101; - let r = _mm512_mask_cmp_epu16_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm512_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!(r, 0b01010101_01010101_01010101_01010101); } From ad387ec57eaf8f5f8c734af8fe9ba887153be031 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:27:28 +0100 Subject: [PATCH 10/73] convert `_mm256_cmp_epu16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 1feebf50bb..9bfc4e9d44 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3728,17 +3728,13 @@ pub unsafe fn _mm512_mask_cmp_epu16_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmp_epu16_mask&expand=713) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm256_cmp_epu16_mask(a: __m256i, b: __m256i, imm8: i32) -> __mmask16 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm256_cmp_epu16_mask(a: __m256i, b: __m256i) -> __mmask16 { + static_assert_imm3!(IMM8); let a = a.as_u16x16(); let b = b.as_u16x16(); - macro_rules! call { - ($imm3:expr) => { - vpcmpuw256(a, b, $imm3, 0b11111111_11111111) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpuw256(a, b, IMM8, 0b11111111_11111111); transmute(r) } @@ -13464,7 +13460,7 @@ mod tests { unsafe fn test_mm256_cmp_epu16_mask() { let a = _mm256_set1_epi16(0); let b = _mm256_set1_epi16(1); - let m = _mm256_cmp_epu16_mask(a, b, _MM_CMPINT_LT); + let m = _mm256_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b); assert_eq!(m, 0b11111111_11111111); } From e6af7a78adbcd8ce62bf3b47f12ee4a61d5955c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:29:17 +0100 Subject: [PATCH 11/73] convert `_mm256_mask_cmp_epu16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 9bfc4e9d44..4df9389029 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3743,22 +3743,17 @@ pub unsafe fn _mm256_cmp_epu16_mask(a: __m256i, b: __m256i) -> /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cmp_epu16_mask&expand=714) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm256_mask_cmp_epu16_mask( +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm256_mask_cmp_epu16_mask( k1: __mmask16, a: __m256i, b: __m256i, - imm8: i32, ) -> __mmask16 { + static_assert_imm3!(IMM8); let a = a.as_u16x16(); let b = b.as_u16x16(); - macro_rules! call { - ($imm3:expr) => { - vpcmpuw256(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpuw256(a, b, IMM8, k1); transmute(r) } @@ -13469,7 +13464,7 @@ mod tests { let a = _mm256_set1_epi16(0); let b = _mm256_set1_epi16(1); let mask = 0b01010101_01010101; - let r = _mm256_mask_cmp_epu16_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm256_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!(r, 0b01010101_01010101); } From 9865abea943798515b85abbba51501a71161082b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:30:13 +0100 Subject: [PATCH 12/73] convert `_mm_cmp_epu16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 4df9389029..74e0ef6c0d 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3762,17 +3762,13 @@ pub unsafe fn _mm256_mask_cmp_epu16_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_epu16_mask&expand=711) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm_cmp_epu16_mask(a: __m128i, b: __m128i, imm8: i32) -> __mmask8 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm_cmp_epu16_mask(a: __m128i, b: __m128i) -> __mmask8 { + static_assert_imm3!(IMM8); let a = a.as_u16x8(); let b = b.as_u16x8(); - macro_rules! call { - ($imm3:expr) => { - vpcmpuw128(a, b, $imm3, 0b11111111) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpuw128(a, b, IMM8, 0b11111111); transmute(r) } @@ -13472,7 +13468,7 @@ mod tests { unsafe fn test_mm_cmp_epu16_mask() { let a = _mm_set1_epi16(0); let b = _mm_set1_epi16(1); - let m = _mm_cmp_epu16_mask(a, b, _MM_CMPINT_LT); + let m = _mm_cmp_epu16_mask::<_MM_CMPINT_LT>(a, b); assert_eq!(m, 0b11111111); } From 417099b0e8092c8017174ae698e2947d81ddc53c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:32:50 +0100 Subject: [PATCH 13/73] convert `_mm_mask_cmp_epu16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 74e0ef6c0d..f7b916d7c0 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3777,17 +3777,17 @@ pub unsafe fn _mm_cmp_epu16_mask(a: __m128i, b: __m128i) -> __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_epu16_mask&expand=712) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm_mask_cmp_epu16_mask(k1: __mmask8, a: __m128i, b: __m128i, imm8: i32) -> __mmask8 { +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm_mask_cmp_epu16_mask( + k1: __mmask8, + a: __m128i, + b: __m128i, +) -> __mmask8 { + static_assert_imm3!(IMM8); let a = a.as_u16x8(); let b = b.as_u16x8(); - macro_rules! call { - ($imm3:expr) => { - vpcmpuw128(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpuw128(a, b, IMM8, k1); transmute(r) } @@ -13477,7 +13477,7 @@ mod tests { let a = _mm_set1_epi16(0); let b = _mm_set1_epi16(1); let mask = 0b01010101; - let r = _mm_mask_cmp_epu16_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm_mask_cmp_epu16_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!(r, 0b01010101); } From 58cf57ccc35dc85b5eff7a1f03985cd9c4048e52 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:33:56 +0100 Subject: [PATCH 14/73] convert `_mm512_cmp_epu8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index f7b916d7c0..4ad3c0901f 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3796,22 +3796,18 @@ pub unsafe fn _mm_mask_cmp_epu16_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_epu8_mask&expand=733) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm512_cmp_epu8_mask(a: __m512i, b: __m512i, imm8: i32) -> __mmask64 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm512_cmp_epu8_mask(a: __m512i, b: __m512i) -> __mmask64 { + static_assert_imm3!(IMM8); let a = a.as_u8x64(); let b = b.as_u8x64(); - macro_rules! call { - ($imm3:expr) => { - vpcmpub( - a, - b, - $imm3, - 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111, - ) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpub( + a, + b, + IMM8, + 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111, + ); transmute(r) } @@ -13485,7 +13481,7 @@ mod tests { unsafe fn test_mm512_cmp_epu8_mask() { let a = _mm512_set1_epi8(0); let b = _mm512_set1_epi8(1); - let m = _mm512_cmp_epu8_mask(a, b, _MM_CMPINT_LT); + let m = _mm512_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b); assert_eq!( m, 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111 From 91ab86e51d0e1a7ede07457b0aa918b8b4fec1ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:35:11 +0100 Subject: [PATCH 15/73] convert `_mm512_mask_cmp_epu8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 4ad3c0901f..51f83f4fa5 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3816,22 +3816,17 @@ pub unsafe fn _mm512_cmp_epu8_mask(a: __m512i, b: __m512i) -> _ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_epu8_mask&expand=734) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm512_mask_cmp_epu8_mask( +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm512_mask_cmp_epu8_mask( k1: __mmask64, a: __m512i, b: __m512i, - imm8: i32, ) -> __mmask64 { + static_assert_imm3!(IMM8); let a = a.as_u8x64(); let b = b.as_u8x64(); - macro_rules! call { - ($imm3:expr) => { - vpcmpub(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpub(a, b, IMM8, k1); transmute(r) } @@ -13493,7 +13488,7 @@ mod tests { let a = _mm512_set1_epi8(0); let b = _mm512_set1_epi8(1); let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101; - let r = _mm512_mask_cmp_epu8_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm512_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!( r, 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101 From c8770975c11f20ea449a31aec1ef96a29b6dba24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:35:57 +0100 Subject: [PATCH 16/73] convert `_mm256_cmp_epu8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 51f83f4fa5..e74b987005 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3835,17 +3835,13 @@ pub unsafe fn _mm512_mask_cmp_epu8_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmp_epu8_mask&expand=731) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm256_cmp_epu8_mask(a: __m256i, b: __m256i, imm8: i32) -> __mmask32 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm256_cmp_epu8_mask(a: __m256i, b: __m256i) -> __mmask32 { + static_assert_imm3!(IMM8); let a = a.as_u8x32(); let b = b.as_u8x32(); - macro_rules! call { - ($imm3:expr) => { - vpcmpub256(a, b, $imm3, 0b11111111_11111111_11111111_11111111) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpub256(a, b, IMM8, 0b11111111_11111111_11111111_11111111); transmute(r) } @@ -13499,7 +13495,7 @@ mod tests { unsafe fn test_mm256_cmp_epu8_mask() { let a = _mm256_set1_epi8(0); let b = _mm256_set1_epi8(1); - let m = _mm256_cmp_epu8_mask(a, b, _MM_CMPINT_LT); + let m = _mm256_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b); assert_eq!(m, 0b11111111_11111111_11111111_11111111); } From 72ef6fc38eb04f1b1a9f54f80b478f834f97a5f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:36:44 +0100 Subject: [PATCH 17/73] convert `_mm256_mask_cmp_epu8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index e74b987005..3905a35227 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3850,22 +3850,17 @@ pub unsafe fn _mm256_cmp_epu8_mask(a: __m256i, b: __m256i) -> _ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cmp_epu8_mask&expand=732) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm256_mask_cmp_epu8_mask( +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm256_mask_cmp_epu8_mask( k1: __mmask32, a: __m256i, b: __m256i, - imm8: i32, ) -> __mmask32 { + static_assert_imm3!(IMM8); let a = a.as_u8x32(); let b = b.as_u8x32(); - macro_rules! call { - ($imm3:expr) => { - vpcmpub256(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpub256(a, b, IMM8, k1); transmute(r) } @@ -13504,7 +13499,7 @@ mod tests { let a = _mm256_set1_epi8(0); let b = _mm256_set1_epi8(1); let mask = 0b01010101_01010101_01010101_01010101; - let r = _mm256_mask_cmp_epu8_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm256_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!(r, 0b01010101_01010101_01010101_01010101); } From 87efe7fd8cb39950cc48950d093404b1b030b0d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:37:38 +0100 Subject: [PATCH 18/73] convert `_mm_cmp_epu8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 3905a35227..4f1c271401 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3869,17 +3869,13 @@ pub unsafe fn _mm256_mask_cmp_epu8_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_epu8_mask&expand=729) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm_cmp_epu8_mask(a: __m128i, b: __m128i, imm8: i32) -> __mmask16 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm_cmp_epu8_mask(a: __m128i, b: __m128i) -> __mmask16 { + static_assert_imm3!(IMM8); let a = a.as_u8x16(); let b = b.as_u8x16(); - macro_rules! call { - ($imm3:expr) => { - vpcmpub128(a, b, $imm3, 0b11111111_11111111) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpub128(a, b, IMM8, 0b11111111_11111111); transmute(r) } @@ -13507,7 +13503,7 @@ mod tests { unsafe fn test_mm_cmp_epu8_mask() { let a = _mm_set1_epi8(0); let b = _mm_set1_epi8(1); - let m = _mm_cmp_epu8_mask(a, b, _MM_CMPINT_LT); + let m = _mm_cmp_epu8_mask::<_MM_CMPINT_LT>(a, b); assert_eq!(m, 0b11111111_11111111); } From 4194761164b18f89191f7d51776a466c716bcff4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:38:29 +0100 Subject: [PATCH 19/73] convert `_mm_mask_cmp_epu8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 4f1c271401..e011cb4749 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3884,22 +3884,17 @@ pub unsafe fn _mm_cmp_epu8_mask(a: __m128i, b: __m128i) -> __mm /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_epu8_mask&expand=730) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm_mask_cmp_epu8_mask( +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm_mask_cmp_epu8_mask( k1: __mmask16, a: __m128i, b: __m128i, - imm8: i32, ) -> __mmask16 { + static_assert_imm3!(IMM8); let a = a.as_u8x16(); let b = b.as_u8x16(); - macro_rules! call { - ($imm3:expr) => { - vpcmpub128(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpub128(a, b, IMM8, k1); transmute(r) } @@ -13512,7 +13507,7 @@ mod tests { let a = _mm_set1_epi8(0); let b = _mm_set1_epi8(1); let mask = 0b01010101_01010101; - let r = _mm_mask_cmp_epu8_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm_mask_cmp_epu8_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!(r, 0b01010101_01010101); } From 180fb1325eaf7d0a3ef164633c15cd0f24ac7d3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:39:20 +0100 Subject: [PATCH 20/73] convert `_mm512_cmp_epi16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index e011cb4749..37b882353b 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3903,17 +3903,13 @@ pub unsafe fn _mm_mask_cmp_epu8_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_epi16_mask&expand=691) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm512_cmp_epi16_mask(a: __m512i, b: __m512i, imm8: i32) -> __mmask32 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm512_cmp_epi16_mask(a: __m512i, b: __m512i) -> __mmask32 { + static_assert_imm3!(IMM8); let a = a.as_i16x32(); let b = b.as_i16x32(); - macro_rules! call { - ($imm3:expr) => { - vpcmpw(a, b, $imm3, 0b11111111_11111111_11111111_11111111) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpw(a, b, IMM8, 0b11111111_11111111_11111111_11111111); transmute(r) } @@ -13515,7 +13511,7 @@ mod tests { unsafe fn test_mm512_cmp_epi16_mask() { let a = _mm512_set1_epi16(0); let b = _mm512_set1_epi16(1); - let m = _mm512_cmp_epi16_mask(a, b, _MM_CMPINT_LT); + let m = _mm512_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b); assert_eq!(m, 0b11111111_11111111_11111111_11111111); } From 5b27c7b88dd7abbdb9b3b38dc4e464ecc78915f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:40:06 +0100 Subject: [PATCH 21/73] convert `_mm512_mask_cmp_epi16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 37b882353b..933e829990 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3918,22 +3918,17 @@ pub unsafe fn _mm512_cmp_epi16_mask(a: __m512i, b: __m512i) -> /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_epi16_mask&expand=692) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm512_mask_cmp_epi16_mask( +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm512_mask_cmp_epi16_mask( k1: __mmask32, a: __m512i, b: __m512i, - imm8: i32, ) -> __mmask32 { + static_assert_imm3!(IMM8); let a = a.as_i16x32(); let b = b.as_i16x32(); - macro_rules! call { - ($imm3:expr) => { - vpcmpw(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpw(a, b, IMM8, k1); transmute(r) } @@ -13520,7 +13515,7 @@ mod tests { let a = _mm512_set1_epi16(0); let b = _mm512_set1_epi16(1); let mask = 0b01010101_01010101_01010101_01010101; - let r = _mm512_mask_cmp_epi16_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm512_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!(r, 0b01010101_01010101_01010101_01010101); } From 9d2e150bed90960e6638cc3a48b0520eca877ad9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:41:44 +0100 Subject: [PATCH 22/73] convert `_mm256_cmp_epi16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 933e829990..a249057a0d 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3937,17 +3937,13 @@ pub unsafe fn _mm512_mask_cmp_epi16_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmp_epi16_mask&expand=689) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm256_cmp_epi16_mask(a: __m256i, b: __m256i, imm8: i32) -> __mmask16 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm256_cmp_epi16_mask(a: __m256i, b: __m256i) -> __mmask16 { + static_assert_imm3!(IMM8); let a = a.as_i16x16(); let b = b.as_i16x16(); - macro_rules! call { - ($imm3:expr) => { - vpcmpw256(a, b, $imm3, 0b11111111_11111111) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpw256(a, b, IMM8, 0b11111111_11111111); transmute(r) } @@ -13523,7 +13519,7 @@ mod tests { unsafe fn test_mm256_cmp_epi16_mask() { let a = _mm256_set1_epi16(0); let b = _mm256_set1_epi16(1); - let m = _mm256_cmp_epi16_mask(a, b, _MM_CMPINT_LT); + let m = _mm256_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b); assert_eq!(m, 0b11111111_11111111); } From 251ee8f2a8e9b6371368ccdb8fbdf8dd7480a8f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:42:46 +0100 Subject: [PATCH 23/73] convert `_mm256_mask_cmp_epi16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index a249057a0d..8bf8dfd1da 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3952,22 +3952,17 @@ pub unsafe fn _mm256_cmp_epi16_mask(a: __m256i, b: __m256i) -> /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cmp_epi16_mask&expand=690) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm256_mask_cmp_epi16_mask( +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm256_mask_cmp_epi16_mask( k1: __mmask16, a: __m256i, b: __m256i, - imm8: i32, ) -> __mmask16 { + static_assert_imm3!(IMM8); let a = a.as_i16x16(); let b = b.as_i16x16(); - macro_rules! call { - ($imm3:expr) => { - vpcmpw256(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpw256(a, b, IMM8, k1); transmute(r) } @@ -13528,7 +13523,7 @@ mod tests { let a = _mm256_set1_epi16(0); let b = _mm256_set1_epi16(1); let mask = 0b01010101_01010101; - let r = _mm256_mask_cmp_epi16_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm256_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!(r, 0b01010101_01010101); } From 43674750c8e88fdbc396ff34e03bead5f57fcf96 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:43:33 +0100 Subject: [PATCH 24/73] convert `_mm_cmp_epi16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 8bf8dfd1da..c905cdf4a6 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3971,17 +3971,13 @@ pub unsafe fn _mm256_mask_cmp_epi16_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_epi16_mask&expand=687) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm_cmp_epi16_mask(a: __m128i, b: __m128i, imm8: i32) -> __mmask8 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm_cmp_epi16_mask(a: __m128i, b: __m128i) -> __mmask8 { + static_assert_imm3!(IMM8); let a = a.as_i16x8(); let b = b.as_i16x8(); - macro_rules! call { - ($imm3:expr) => { - vpcmpw128(a, b, $imm3, 0b11111111) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpw128(a, b, IMM8, 0b11111111); transmute(r) } @@ -13531,7 +13527,7 @@ mod tests { unsafe fn test_mm_cmp_epi16_mask() { let a = _mm_set1_epi16(0); let b = _mm_set1_epi16(1); - let m = _mm_cmp_epi16_mask(a, b, _MM_CMPINT_LT); + let m = _mm_cmp_epi16_mask::<_MM_CMPINT_LT>(a, b); assert_eq!(m, 0b11111111); } From 6daf45754a80d5b2137ca67116fe1137d2c84140 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:44:18 +0100 Subject: [PATCH 25/73] convert `_mm_mask_cmp_epi16_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index c905cdf4a6..e2cfe4b0ac 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -3986,17 +3986,17 @@ pub unsafe fn _mm_cmp_epi16_mask(a: __m128i, b: __m128i) -> __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_epi16_mask&expand=688) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm_mask_cmp_epi16_mask(k1: __mmask8, a: __m128i, b: __m128i, imm8: i32) -> __mmask8 { +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm_mask_cmp_epi16_mask( + k1: __mmask8, + a: __m128i, + b: __m128i, +) -> __mmask8 { + static_assert_imm3!(IMM8); let a = a.as_i16x8(); let b = b.as_i16x8(); - macro_rules! call { - ($imm3:expr) => { - vpcmpw128(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpw128(a, b, IMM8, k1); transmute(r) } @@ -13536,7 +13536,7 @@ mod tests { let a = _mm_set1_epi16(0); let b = _mm_set1_epi16(1); let mask = 0b01010101; - let r = _mm_mask_cmp_epi16_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm_mask_cmp_epi16_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!(r, 0b01010101); } From 3328d52d985c6d94d1df3b6085888687a0022a1a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:44:58 +0100 Subject: [PATCH 26/73] convert `_mm512_cmp_epi8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index e2cfe4b0ac..59e6372711 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -4005,22 +4005,18 @@ pub unsafe fn _mm_mask_cmp_epi16_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_cmp_epi8_mask&expand=709) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm512_cmp_epi8_mask(a: __m512i, b: __m512i, imm8: i32) -> __mmask64 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm512_cmp_epi8_mask(a: __m512i, b: __m512i) -> __mmask64 { + static_assert_imm3!(IMM8); let a = a.as_i8x64(); let b = b.as_i8x64(); - macro_rules! call { - ($imm3:expr) => { - vpcmpb( - a, - b, - $imm3, - 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111, - ) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpb( + a, + b, + IMM8, + 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111, + ); transmute(r) } @@ -13544,7 +13540,7 @@ mod tests { unsafe fn test_mm512_cmp_epi8_mask() { let a = _mm512_set1_epi8(0); let b = _mm512_set1_epi8(1); - let m = _mm512_cmp_epi8_mask(a, b, _MM_CMPINT_LT); + let m = _mm512_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b); assert_eq!( m, 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111 From eb6db979a8d42ebdbd411e053337446a14b7b2b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:46:06 +0100 Subject: [PATCH 27/73] convert `_mm512_mask_cmp_epi8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 59e6372711..b0da4936d7 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -4025,22 +4025,17 @@ pub unsafe fn _mm512_cmp_epi8_mask(a: __m512i, b: __m512i) -> _ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_cmp_epi8_mask&expand=710) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm512_mask_cmp_epi8_mask( +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm512_mask_cmp_epi8_mask( k1: __mmask64, a: __m512i, b: __m512i, - imm8: i32, ) -> __mmask64 { + static_assert_imm3!(IMM8); let a = a.as_i8x64(); let b = b.as_i8x64(); - macro_rules! call { - ($imm3:expr) => { - vpcmpb(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpb(a, b, IMM8, k1); transmute(r) } @@ -13552,7 +13547,7 @@ mod tests { let a = _mm512_set1_epi8(0); let b = _mm512_set1_epi8(1); let mask = 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101; - let r = _mm512_mask_cmp_epi8_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm512_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!( r, 0b01010101_01010101_01010101_01010101_01010101_01010101_01010101_01010101 From 7c2e525bb3f7331e83a276446a05f308663ed9ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:46:52 +0100 Subject: [PATCH 28/73] convert `_mm256_cmp_epi8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index b0da4936d7..cdf049b1ce 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -4044,17 +4044,13 @@ pub unsafe fn _mm512_mask_cmp_epi8_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_cmp_epi8_mask&expand=707) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm256_cmp_epi8_mask(a: __m256i, b: __m256i, imm8: i32) -> __mmask32 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm256_cmp_epi8_mask(a: __m256i, b: __m256i) -> __mmask32 { + static_assert_imm3!(IMM8); let a = a.as_i8x32(); let b = b.as_i8x32(); - macro_rules! call { - ($imm3:expr) => { - vpcmpb256(a, b, $imm3, 0b11111111_11111111_11111111_11111111) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpb256(a, b, IMM8, 0b11111111_11111111_11111111_11111111); transmute(r) } @@ -13558,7 +13554,7 @@ mod tests { unsafe fn test_mm256_cmp_epi8_mask() { let a = _mm256_set1_epi8(0); let b = _mm256_set1_epi8(1); - let m = _mm256_cmp_epi8_mask(a, b, _MM_CMPINT_LT); + let m = _mm256_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b); assert_eq!(m, 0b11111111_11111111_11111111_11111111); } From d248792417ff4ff487c63c79e60a49898a34a4e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:47:40 +0100 Subject: [PATCH 29/73] convert `_mm256_mask_cmp_epi8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index cdf049b1ce..cb1cd29c92 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -4059,22 +4059,17 @@ pub unsafe fn _mm256_cmp_epi8_mask(a: __m256i, b: __m256i) -> _ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_cmp_epi8_mask&expand=708) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm256_mask_cmp_epi8_mask( +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm256_mask_cmp_epi8_mask( k1: __mmask32, a: __m256i, b: __m256i, - imm8: i32, ) -> __mmask32 { + static_assert_imm3!(IMM8); let a = a.as_i8x32(); let b = b.as_i8x32(); - macro_rules! call { - ($imm3:expr) => { - vpcmpb256(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpb256(a, b, IMM8, k1); transmute(r) } @@ -13563,7 +13558,7 @@ mod tests { let a = _mm256_set1_epi8(0); let b = _mm256_set1_epi8(1); let mask = 0b01010101_01010101_01010101_01010101; - let r = _mm256_mask_cmp_epi8_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm256_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!(r, 0b01010101_01010101_01010101_01010101); } From be531e5ec9dbce80e7a328cd72d8fbde186f79d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:48:46 +0100 Subject: [PATCH 30/73] convert `_mm_cmp_epi8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index cb1cd29c92..93de2e0514 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -4078,17 +4078,13 @@ pub unsafe fn _mm256_mask_cmp_epi8_mask( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmp_epi8_mask&expand=705) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm_cmp_epi8_mask(a: __m128i, b: __m128i, imm8: i32) -> __mmask16 { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm_cmp_epi8_mask(a: __m128i, b: __m128i) -> __mmask16 { + static_assert_imm3!(IMM8); let a = a.as_i8x16(); let b = b.as_i8x16(); - macro_rules! call { - ($imm3:expr) => { - vpcmpb128(a, b, $imm3, 0b11111111_11111111) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpb128(a, b, IMM8, 0b11111111_11111111); transmute(r) } @@ -13566,7 +13562,7 @@ mod tests { unsafe fn test_mm_cmp_epi8_mask() { let a = _mm_set1_epi8(0); let b = _mm_set1_epi8(1); - let m = _mm_cmp_epi8_mask(a, b, _MM_CMPINT_LT); + let m = _mm_cmp_epi8_mask::<_MM_CMPINT_LT>(a, b); assert_eq!(m, 0b11111111_11111111); } From 0617c2f07b1874ba6906882747e1b05f65d86acb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 22:49:27 +0100 Subject: [PATCH 31/73] convert `_mm_mask_cmp_epi8_mask` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 93de2e0514..5f48d76cb7 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -4093,22 +4093,17 @@ pub unsafe fn _mm_cmp_epi8_mask(a: __m128i, b: __m128i) -> __mm /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_cmp_epi8_mask&expand=706) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpcmp, imm8 = 0))] -pub unsafe fn _mm_mask_cmp_epi8_mask( +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpcmp, IMM8 = 0))] +pub unsafe fn _mm_mask_cmp_epi8_mask( k1: __mmask16, a: __m128i, b: __m128i, - imm8: i32, ) -> __mmask16 { + static_assert_imm3!(IMM8); let a = a.as_i8x16(); let b = b.as_i8x16(); - macro_rules! call { - ($imm3:expr) => { - vpcmpb128(a, b, $imm3, k1) - }; - } - let r = constify_imm3!(imm8, call); + let r = vpcmpb128(a, b, IMM8, k1); transmute(r) } @@ -13571,7 +13566,7 @@ mod tests { let a = _mm_set1_epi8(0); let b = _mm_set1_epi8(1); let mask = 0b01010101_01010101; - let r = _mm_mask_cmp_epi8_mask(mask, a, b, _MM_CMPINT_LT); + let r = _mm_mask_cmp_epi8_mask::<_MM_CMPINT_LT>(mask, a, b); assert_eq!(r, 0b01010101_01010101); } From 9f97c68caafbb2915dfda7e67eb6fa4f2f526ea5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 23:23:51 +0100 Subject: [PATCH 32/73] convert `_mm512_slli_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- crates/core_arch/src/x86/macros.rs | 17 +++++++++++++++++ 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 5f48d76cb7..61614f8ff3 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5008,16 +5008,12 @@ pub unsafe fn _mm_maskz_sll_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_slli_epi16&expand=5301) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpsllw, imm8 = 5))] -#[rustc_args_required_const(1)] -pub unsafe fn _mm512_slli_epi16(a: __m512i, imm8: u32) -> __m512i { +#[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))] +#[rustc_legacy_const_generics(1)] +pub unsafe fn _mm512_slli_epi16(a: __m512i) -> __m512i { + static_assert_imm_u8!(IMM8); let a = a.as_i16x32(); - macro_rules! call { - ($imm8:expr) => { - vpslliw(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vpslliw(a, IMM8); transmute(r) } @@ -14476,7 +14472,7 @@ mod tests { #[simd_test(enable = "avx512bw")] unsafe fn test_mm512_slli_epi16() { let a = _mm512_set1_epi16(1 << 15); - let r = _mm512_slli_epi16(a, 1); + let r = _mm512_slli_epi16::<1>(a); let e = _mm512_set1_epi16(0); assert_eq_m512i(r, e); } diff --git a/crates/core_arch/src/x86/macros.rs b/crates/core_arch/src/x86/macros.rs index d4c8e363ba..c22328024b 100644 --- a/crates/core_arch/src/x86/macros.rs +++ b/crates/core_arch/src/x86/macros.rs @@ -32,6 +32,23 @@ macro_rules! static_assert_sae { }; } +// Helper struct used to trigger const eval errors when the unsigned const generic immediate value +// `IMM` is out of `[MIN-MAX]` range. +pub(crate) struct ValidateConstImmU32; +impl ValidateConstImmU32 { + pub(crate) const VALID: () = { + let _ = 1 / ((IMM >= MIN && IMM <= MAX) as usize); + }; +} + +#[allow(unused_macros)] +macro_rules! static_assert_imm_u8 { + ($imm:ident) => { + let _ = + $crate::core_arch::x86::macros::ValidateConstImmU32::<$imm, 0, { (1 << 8) - 1 }>::VALID; + }; +} + macro_rules! constify_imm3 { ($imm8:expr, $expand:ident) => { #[allow(overflowing_literals)] From 9bd0e812864b81419a26388af7d87c1346ba841a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 23:27:08 +0100 Subject: [PATCH 33/73] convert `_mm512_mask_slli_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 61614f8ff3..dd0790bf86 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5022,16 +5022,16 @@ pub unsafe fn _mm512_slli_epi16(a: __m512i) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_slli_epi16&expand=5299) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpsllw, imm8 = 5))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_mask_slli_epi16(src: __m512i, k: __mmask32, a: __m512i, imm8: u32) -> __m512i { +#[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_mask_slli_epi16( + src: __m512i, + k: __mmask32, + a: __m512i, +) -> __m512i { + static_assert_imm_u8!(IMM8); let a = a.as_i16x32(); - macro_rules! call { - ($imm8:expr) => { - vpslliw(a, $imm8) - }; - } - let shf = constify_imm8_sae!(imm8, call); + let shf = vpslliw(a, IMM8); transmute(simd_select_bitmask(k, shf, src.as_i16x32())) } @@ -14480,9 +14480,9 @@ mod tests { #[simd_test(enable = "avx512bw")] unsafe fn test_mm512_mask_slli_epi16() { let a = _mm512_set1_epi16(1 << 15); - let r = _mm512_mask_slli_epi16(a, 0, a, 1); + let r = _mm512_mask_slli_epi16::<1>(a, 0, a); assert_eq_m512i(r, a); - let r = _mm512_mask_slli_epi16(a, 0b11111111_11111111_11111111_11111111, a, 1); + let r = _mm512_mask_slli_epi16::<1>(a, 0b11111111_11111111_11111111_11111111, a); let e = _mm512_set1_epi16(0); assert_eq_m512i(r, e); } From 21688a9155dd9088c13498c7a66455b3ec73a7c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 23:28:48 +0100 Subject: [PATCH 34/73] convert `_mm512_maskz_slli_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index dd0790bf86..1589bd4b95 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5040,16 +5040,12 @@ pub unsafe fn _mm512_mask_slli_epi16( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_slli_epi16&expand=5300) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpsllw, imm8 = 5))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm512_maskz_slli_epi16(k: __mmask32, a: __m512i, imm8: u32) -> __m512i { +#[cfg_attr(test, assert_instr(vpsllw, IMM8 = 5))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm512_maskz_slli_epi16(k: __mmask32, a: __m512i) -> __m512i { + static_assert_imm_u8!(IMM8); let a = a.as_i16x32(); - macro_rules! call { - ($imm8:expr) => { - vpslliw(a, $imm8) - }; - } - let shf = constify_imm8_sae!(imm8, call); + let shf = vpslliw(a, IMM8); let zero = _mm512_setzero_si512().as_i16x32(); transmute(simd_select_bitmask(k, shf, zero)) } @@ -14490,9 +14486,9 @@ mod tests { #[simd_test(enable = "avx512bw")] unsafe fn test_mm512_maskz_slli_epi16() { let a = _mm512_set1_epi16(1 << 15); - let r = _mm512_maskz_slli_epi16(0, a, 1); + let r = _mm512_maskz_slli_epi16::<1>(0, a); assert_eq_m512i(r, _mm512_setzero_si512()); - let r = _mm512_maskz_slli_epi16(0b11111111_11111111_11111111_11111111, a, 1); + let r = _mm512_maskz_slli_epi16::<1>(0b11111111_11111111_11111111_11111111, a); let e = _mm512_set1_epi16(0); assert_eq_m512i(r, e); } From 2f4974e974bd3ed613262e355da9246586cb845c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:08:24 +0100 Subject: [PATCH 35/73] convert `_mm512_srli_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 1589bd4b95..1c863a6d10 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5328,16 +5328,12 @@ pub unsafe fn _mm_maskz_srl_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srli_epi16&expand=5513) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 5))] -#[rustc_args_required_const(1)] -pub unsafe fn _mm512_srli_epi16(a: __m512i, imm8: u32) -> __m512i { +#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] +#[rustc_legacy_const_generics(1)] +pub unsafe fn _mm512_srli_epi16(a: __m512i) -> __m512i { + static_assert_imm_u8!(IMM8); let a = a.as_i16x32(); - macro_rules! call { - ($imm8:expr) => { - vpsrliw(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vpsrliw(a, IMM8); transmute(r) } @@ -14704,7 +14700,7 @@ mod tests { #[simd_test(enable = "avx512bw")] unsafe fn test_mm512_srli_epi16() { let a = _mm512_set1_epi16(1 << 1); - let r = _mm512_srli_epi16(a, 2); + let r = _mm512_srli_epi16::<2>(a); let e = _mm512_set1_epi16(0); assert_eq_m512i(r, e); } From 738d2e27f62dfc59096452ac509a5c90229b8a17 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:09:50 +0100 Subject: [PATCH 36/73] convert `_mm512_mask_srli_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 1c863a6d10..ccd5d27a3d 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5342,16 +5342,16 @@ pub unsafe fn _mm512_srli_epi16(a: __m512i) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srli_epi16&expand=5511) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 5))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_mask_srli_epi16(src: __m512i, k: __mmask32, a: __m512i, imm8: u32) -> __m512i { +#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_mask_srli_epi16( + src: __m512i, + k: __mmask32, + a: __m512i, +) -> __m512i { + static_assert_imm_u8!(IMM8); let a = a.as_i16x32(); - macro_rules! call { - ($imm8:expr) => { - vpsrliw(a, $imm8) - }; - } - let shf = constify_imm8_sae!(imm8, call); + let shf = vpsrliw(a, IMM8); transmute(simd_select_bitmask(k, shf, src.as_i16x32())) } @@ -14708,9 +14708,9 @@ mod tests { #[simd_test(enable = "avx512bw")] unsafe fn test_mm512_mask_srli_epi16() { let a = _mm512_set1_epi16(1 << 1); - let r = _mm512_mask_srli_epi16(a, 0, a, 2); + let r = _mm512_mask_srli_epi16::<2>(a, 0, a); assert_eq_m512i(r, a); - let r = _mm512_mask_srli_epi16(a, 0b11111111_11111111_11111111_11111111, a, 2); + let r = _mm512_mask_srli_epi16::<2>(a, 0b11111111_11111111_11111111_11111111, a); let e = _mm512_set1_epi16(0); assert_eq_m512i(r, e); } From 82e584e8a0a6187a8cedb7cccce4434bc648e455 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:14:10 +0100 Subject: [PATCH 37/73] convert `_mm512_maskz_srli_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index ccd5d27a3d..8c5e176f7c 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5360,17 +5360,13 @@ pub unsafe fn _mm512_mask_srli_epi16( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srli_epi16&expand=5512) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 5))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm512_maskz_srli_epi16(k: __mmask32, a: __m512i, imm8: i32) -> __m512i { +#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm512_maskz_srli_epi16(k: __mmask32, a: __m512i) -> __m512i { + static_assert_imm8!(IMM8); //imm8 should be u32, it seems the document to verify is incorrect let a = a.as_i16x32(); - macro_rules! call { - ($imm8:expr) => { - vpsrliw(a, $imm8) - }; - } - let shf = constify_imm8_sae!(imm8, call); + let shf = vpsrliw(a, IMM8 as u32); let zero = _mm512_setzero_si512().as_i16x32(); transmute(simd_select_bitmask(k, shf, zero)) } @@ -14718,9 +14714,9 @@ mod tests { #[simd_test(enable = "avx512bw")] unsafe fn test_mm512_maskz_srli_epi16() { let a = _mm512_set1_epi16(1 << 1); - let r = _mm512_maskz_srli_epi16(0, a, 2); + let r = _mm512_maskz_srli_epi16::<2>(0, a); assert_eq_m512i(r, _mm512_setzero_si512()); - let r = _mm512_maskz_srli_epi16(0b11111111_11111111_11111111_11111111, a, 2); + let r = _mm512_maskz_srli_epi16::<2>(0b11111111_11111111_11111111_11111111, a); let e = _mm512_set1_epi16(0); assert_eq_m512i(r, e); } From 5c3fea114337bee5eb42033be77f094752207e72 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:16:50 +0100 Subject: [PATCH 38/73] convert `_mm256_mask_srli_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 8c5e176f7c..9bb15db5e5 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5376,15 +5376,15 @@ pub unsafe fn _mm512_maskz_srli_epi16(k: __mmask32, a: __m512i) /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_srli_epi16&expand=5508) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 5))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm256_mask_srli_epi16(src: __m256i, k: __mmask16, a: __m256i, imm8: i32) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_srli_epi16::<$imm8>(a) - }; - } - let shf = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm256_mask_srli_epi16( + src: __m256i, + k: __mmask16, + a: __m256i, +) -> __m256i { + static_assert_imm8!(IMM8); + let shf = _mm256_srli_epi16::(a); transmute(simd_select_bitmask(k, shf.as_i16x16(), src.as_i16x16())) } @@ -14724,9 +14724,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm256_mask_srli_epi16() { let a = _mm256_set1_epi16(1 << 1); - let r = _mm256_mask_srli_epi16(a, 0, a, 2); + let r = _mm256_mask_srli_epi16::<2>(a, 0, a); assert_eq_m256i(r, a); - let r = _mm256_mask_srli_epi16(a, 0b11111111_11111111, a, 2); + let r = _mm256_mask_srli_epi16::<2>(a, 0b11111111_11111111, a); let e = _mm256_set1_epi16(0); assert_eq_m256i(r, e); } From 202b4cadb3fae2009cec0d7eff680dbe02e791b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:26:51 +0100 Subject: [PATCH 39/73] convert `_mm256_maskz_srli_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 9bb15db5e5..6a9a29985d 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5393,15 +5393,11 @@ pub unsafe fn _mm256_mask_srli_epi16( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_srli_epi16&expand=5509) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 5))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm256_maskz_srli_epi16(k: __mmask16, a: __m256i, imm8: i32) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_srli_epi16::<$imm8>(a) - }; - } - let shf = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm256_maskz_srli_epi16(k: __mmask16, a: __m256i) -> __m256i { + static_assert_imm8!(IMM8); + let shf = _mm256_srli_epi16::(a); let zero = _mm256_setzero_si256().as_i16x16(); transmute(simd_select_bitmask(k, shf.as_i16x16(), zero)) } @@ -14734,9 +14730,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm256_maskz_srli_epi16() { let a = _mm256_set1_epi16(1 << 1); - let r = _mm256_maskz_srli_epi16(0, a, 2); + let r = _mm256_maskz_srli_epi16::<2>(0, a); assert_eq_m256i(r, _mm256_setzero_si256()); - let r = _mm256_maskz_srli_epi16(0b11111111_11111111, a, 2); + let r = _mm256_maskz_srli_epi16::<2>(0b11111111_11111111, a); let e = _mm256_set1_epi16(0); assert_eq_m256i(r, e); } From f8b9ddfcd13434192ffef69e3a98f37047e5936b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:28:27 +0100 Subject: [PATCH 40/73] convert `_mm_mask_srli_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 6a9a29985d..ba88db340f 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5407,15 +5407,15 @@ pub unsafe fn _mm256_maskz_srli_epi16(k: __mmask16, a: __m256i) /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_srli_epi16&expand=5505) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 5))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm_mask_srli_epi16(src: __m128i, k: __mmask8, a: __m128i, imm8: i32) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_srli_epi16::<$imm8>(a) - }; - } - let shf = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm_mask_srli_epi16( + src: __m128i, + k: __mmask8, + a: __m128i, +) -> __m128i { + static_assert_imm8!(IMM8); + let shf = _mm_srli_epi16::(a); transmute(simd_select_bitmask(k, shf.as_i16x8(), src.as_i16x8())) } @@ -14740,9 +14740,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm_mask_srli_epi16() { let a = _mm_set1_epi16(1 << 1); - let r = _mm_mask_srli_epi16(a, 0, a, 2); + let r = _mm_mask_srli_epi16::<2>(a, 0, a); assert_eq_m128i(r, a); - let r = _mm_mask_srli_epi16(a, 0b11111111, a, 2); + let r = _mm_mask_srli_epi16::<2>(a, 0b11111111, a); let e = _mm_set1_epi16(0); assert_eq_m128i(r, e); } From 236e9feebe2a541d27c815652ae27545c8371df0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:30:12 +0100 Subject: [PATCH 41/73] convert `_mm_maskz_srli_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index ba88db340f..fa954a64d4 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5424,15 +5424,11 @@ pub unsafe fn _mm_mask_srli_epi16( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_srli_epi16&expand=5506) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpsrlw, imm8 = 5))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm_maskz_srli_epi16(k: __mmask8, a: __m128i, imm8: i32) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_srli_epi16::<$imm8>(a) - }; - } - let shf = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpsrlw, IMM8 = 5))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm_maskz_srli_epi16(k: __mmask8, a: __m128i) -> __m128i { + static_assert_imm8!(IMM8); + let shf = _mm_srli_epi16::(a); let zero = _mm_setzero_si128().as_i16x8(); transmute(simd_select_bitmask(k, shf.as_i16x8(), zero)) } @@ -14750,9 +14746,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm_maskz_srli_epi16() { let a = _mm_set1_epi16(1 << 1); - let r = _mm_maskz_srli_epi16(0, a, 2); + let r = _mm_maskz_srli_epi16::<2>(0, a); assert_eq_m128i(r, _mm_setzero_si128()); - let r = _mm_maskz_srli_epi16(0b11111111, a, 2); + let r = _mm_maskz_srli_epi16::<2>(0b11111111, a); let e = _mm_set1_epi16(0); assert_eq_m128i(r, e); } From 3a5ecf1c2fdb8de053e87b1722f3dd4453726581 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:32:19 +0100 Subject: [PATCH 42/73] convert `_mm512_srai_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index fa954a64d4..fb9de3db10 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5641,16 +5641,12 @@ pub unsafe fn _mm_maskz_sra_epi16(k: __mmask8, a: __m128i, count: __m128i) -> __ /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_srai_epi16&expand=5427) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpsraw, imm8 = 1))] -#[rustc_args_required_const(1)] -pub unsafe fn _mm512_srai_epi16(a: __m512i, imm8: u32) -> __m512i { +#[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))] +#[rustc_legacy_const_generics(1)] +pub unsafe fn _mm512_srai_epi16(a: __m512i) -> __m512i { + static_assert_imm_u8!(IMM8); let a = a.as_i16x32(); - macro_rules! call { - ($imm8:expr) => { - vpsraiw(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vpsraiw(a, IMM8); transmute(r) } @@ -14924,7 +14920,7 @@ mod tests { #[simd_test(enable = "avx512bw")] unsafe fn test_mm512_srai_epi16() { let a = _mm512_set1_epi16(8); - let r = _mm512_srai_epi16(a, 2); + let r = _mm512_srai_epi16::<2>(a); let e = _mm512_set1_epi16(2); assert_eq_m512i(r, e); } From db3c11915b9c7bb9e08d2c30e6d4db168c92b851 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:33:59 +0100 Subject: [PATCH 43/73] convert `_mm512_mask_srai_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index fb9de3db10..f977225cbb 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5655,16 +5655,16 @@ pub unsafe fn _mm512_srai_epi16(a: __m512i) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_srai_epi16&expand=5425) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpsraw, imm8 = 1))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_mask_srai_epi16(src: __m512i, k: __mmask32, a: __m512i, imm8: u32) -> __m512i { +#[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_mask_srai_epi16( + src: __m512i, + k: __mmask32, + a: __m512i, +) -> __m512i { + static_assert_imm_u8!(IMM8); let a = a.as_i16x32(); - macro_rules! call { - ($imm8:expr) => { - vpsraiw(a, $imm8) - }; - } - let shf = constify_imm8_sae!(imm8, call); + let shf = vpsraiw(a, IMM8); transmute(simd_select_bitmask(k, shf, src.as_i16x32())) } @@ -14928,9 +14928,9 @@ mod tests { #[simd_test(enable = "avx512bw")] unsafe fn test_mm512_mask_srai_epi16() { let a = _mm512_set1_epi16(8); - let r = _mm512_mask_srai_epi16(a, 0, a, 2); + let r = _mm512_mask_srai_epi16::<2>(a, 0, a); assert_eq_m512i(r, a); - let r = _mm512_mask_srai_epi16(a, 0b11111111_11111111_11111111_11111111, a, 2); + let r = _mm512_mask_srai_epi16::<2>(a, 0b11111111_11111111_11111111_11111111, a); let e = _mm512_set1_epi16(2); assert_eq_m512i(r, e); } From 6233708b06e7a800c1958752ffb08bf5b7b86580 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:35:09 +0100 Subject: [PATCH 44/73] convert `_mm512_maskz_srai_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index f977225cbb..960cb98e2e 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -5673,16 +5673,12 @@ pub unsafe fn _mm512_mask_srai_epi16( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_srai_epi16&expand=5426) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpsraw, imm8 = 1))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm512_maskz_srai_epi16(k: __mmask32, a: __m512i, imm8: u32) -> __m512i { +#[cfg_attr(test, assert_instr(vpsraw, IMM8 = 1))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm512_maskz_srai_epi16(k: __mmask32, a: __m512i) -> __m512i { + static_assert_imm_u8!(IMM8); let a = a.as_i16x32(); - macro_rules! call { - ($imm8:expr) => { - vpsraiw(a, $imm8) - }; - } - let shf = constify_imm8_sae!(imm8, call); + let shf = vpsraiw(a, IMM8); let zero = _mm512_setzero_si512().as_i16x32(); transmute(simd_select_bitmask(k, shf, zero)) } @@ -14938,9 +14934,9 @@ mod tests { #[simd_test(enable = "avx512bw")] unsafe fn test_mm512_maskz_srai_epi16() { let a = _mm512_set1_epi16(8); - let r = _mm512_maskz_srai_epi16(0, a, 2); + let r = _mm512_maskz_srai_epi16::<2>(0, a); assert_eq_m512i(r, _mm512_setzero_si512()); - let r = _mm512_maskz_srai_epi16(0b11111111_11111111_11111111_11111111, a, 2); + let r = _mm512_maskz_srai_epi16::<2>(0b11111111_11111111_11111111_11111111, a); let e = _mm512_set1_epi16(2); assert_eq_m512i(r, e); } From af3ca25f5cd410ffca640623127fe5526ac1e3da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:42:07 +0100 Subject: [PATCH 45/73] convert `_mm512_mask_shufflelo_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 960cb98e2e..3348dff88a 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7194,20 +7194,15 @@ pub unsafe fn _mm512_shufflelo_epi16(a: __m512i, imm8: i32) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shufflelo_epi16&expand=5219) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpshuflw, imm8 = 0))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_mask_shufflelo_epi16( +#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 0))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_mask_shufflelo_epi16( src: __m512i, k: __mmask32, a: __m512i, - imm8: i32, ) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_shufflelo_epi16(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm512_shufflelo_epi16(a, IMM8); transmute(simd_select_bitmask(k, r.as_i16x32(), src.as_i16x32())) } @@ -16332,10 +16327,13 @@ mod tests { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, ); - let r = _mm512_mask_shufflelo_epi16(a, 0, a, 0b00_01_01_11); + let r = _mm512_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0, a); assert_eq_m512i(r, a); - let r = - _mm512_mask_shufflelo_epi16(a, 0b11111111_11111111_11111111_11111111, a, 0b00_01_01_11); + let r = _mm512_mask_shufflelo_epi16::<0b00_01_01_11>( + a, + 0b11111111_11111111_11111111_11111111, + a, + ); #[rustfmt::skip] let e = _mm512_set_epi16( 0, 1, 2, 3, 7, 6, 6, 4, 8, 9, 10, 11, 15, 14, 14, 12, From 43c346290a39be67b1d8bcd808ea9dda8af4daea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:43:26 +0100 Subject: [PATCH 46/73] convert `_mm512_maskz_shufflelo_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 3348dff88a..7ecbc8a9ef 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7211,15 +7211,11 @@ pub unsafe fn _mm512_mask_shufflelo_epi16( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shufflelo_epi16&expand=5220) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpshuflw, imm8 = 0))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm512_maskz_shufflelo_epi16(k: __mmask32, a: __m512i, imm8: i32) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_shufflelo_epi16(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm512_maskz_shufflelo_epi16(k: __mmask32, a: __m512i) -> __m512i { + static_assert_imm8!(IMM8); + let r = _mm512_shufflelo_epi16(a, IMM8); let zero = _mm512_setzero_si512().as_i16x32(); transmute(simd_select_bitmask(k, r.as_i16x32(), zero)) } @@ -16349,10 +16345,10 @@ mod tests { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, ); - let r = _mm512_maskz_shufflelo_epi16(0, a, 0b00_01_01_11); + let r = _mm512_maskz_shufflelo_epi16::<0b00_01_01_11>(0, a); assert_eq_m512i(r, _mm512_setzero_si512()); let r = - _mm512_maskz_shufflelo_epi16(0b11111111_11111111_11111111_11111111, a, 0b00_01_01_11); + _mm512_maskz_shufflelo_epi16::<0b00_01_01_11>(0b11111111_11111111_11111111_11111111, a); #[rustfmt::skip] let e = _mm512_set_epi16( 0, 1, 2, 3, 7, 6, 6, 4, 8, 9, 10, 11, 15, 14, 14, 12, From 02f1e0a9668da764f2c038265d4ec177b6eb1b15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:44:34 +0100 Subject: [PATCH 47/73] convert `_mm256_mask_shufflelo_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 7ecbc8a9ef..80290225bd 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7225,20 +7225,15 @@ pub unsafe fn _mm512_maskz_shufflelo_epi16(k: __mmask32, a: __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_shufflelo_epi16&expand=5216) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpshuflw, imm8 = 5))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm256_mask_shufflelo_epi16( +#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm256_mask_shufflelo_epi16( src: __m256i, k: __mmask16, a: __m256i, - imm8: i32, ) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_shufflelo_epi16(a, $imm8) - }; - } - let shuffle = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let shuffle = _mm256_shufflelo_epi16(a, IMM8); transmute(simd_select_bitmask(k, shuffle.as_i16x16(), src.as_i16x16())) } @@ -16360,9 +16355,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm256_mask_shufflelo_epi16() { let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r = _mm256_mask_shufflelo_epi16(a, 0, a, 0b00_01_01_11); + let r = _mm256_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0, a); assert_eq_m256i(r, a); - let r = _mm256_mask_shufflelo_epi16(a, 0b11111111_11111111, a, 0b00_01_01_11); + let r = _mm256_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0b11111111_11111111, a); let e = _mm256_set_epi16(0, 1, 2, 3, 7, 6, 6, 4, 8, 9, 10, 11, 15, 14, 14, 12); assert_eq_m256i(r, e); } From 3a4eef9b65352b69aa2cd5759acd2fc92ecda97b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:45:15 +0100 Subject: [PATCH 48/73] convert `_mm256_maskz_shufflelo_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 80290225bd..716e14da36 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7242,15 +7242,11 @@ pub unsafe fn _mm256_mask_shufflelo_epi16( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_shufflelo_epi16&expand=5217) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpshuflw, imm8 = 5))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm256_maskz_shufflelo_epi16(k: __mmask16, a: __m256i, imm8: i32) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_shufflelo_epi16(a, $imm8) - }; - } - let shuffle = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm256_maskz_shufflelo_epi16(k: __mmask16, a: __m256i) -> __m256i { + static_assert_imm8!(IMM8); + let shuffle = _mm256_shufflelo_epi16(a, IMM8); let zero = _mm256_setzero_si256().as_i16x16(); transmute(simd_select_bitmask(k, shuffle.as_i16x16(), zero)) } @@ -16365,9 +16361,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm256_maskz_shufflelo_epi16() { let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r = _mm256_maskz_shufflelo_epi16(0, a, 0b00_01_01_11); + let r = _mm256_maskz_shufflelo_epi16::<0b00_01_01_11>(0, a); assert_eq_m256i(r, _mm256_setzero_si256()); - let r = _mm256_maskz_shufflelo_epi16(0b11111111_11111111, a, 0b00_01_01_11); + let r = _mm256_maskz_shufflelo_epi16::<0b00_01_01_11>(0b11111111_11111111, a); let e = _mm256_set_epi16(0, 1, 2, 3, 7, 6, 6, 4, 8, 9, 10, 11, 15, 14, 14, 12); assert_eq_m256i(r, e); } From dc096ceccefcd255593141e94f21fc63080a4e33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:46:48 +0100 Subject: [PATCH 49/73] convert `_mm_mask_shufflelo_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 716e14da36..48647ec156 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7256,20 +7256,15 @@ pub unsafe fn _mm256_maskz_shufflelo_epi16(k: __mmask16, a: __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_shufflelo_epi16&expand=5213) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpshuflw, imm8 = 5))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm_mask_shufflelo_epi16( +#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm_mask_shufflelo_epi16( src: __m128i, k: __mmask8, a: __m128i, - imm8: i32, ) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_shufflelo_epi16::<$imm8>(a) - }; - } - let shuffle = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let shuffle = _mm_shufflelo_epi16::(a); transmute(simd_select_bitmask(k, shuffle.as_i16x8(), src.as_i16x8())) } @@ -16371,9 +16366,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm_mask_shufflelo_epi16() { let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7); - let r = _mm_mask_shufflelo_epi16(a, 0, a, 0b00_01_01_11); + let r = _mm_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0, a); assert_eq_m128i(r, a); - let r = _mm_mask_shufflelo_epi16(a, 0b11111111, a, 0b00_01_01_11); + let r = _mm_mask_shufflelo_epi16::<0b00_01_01_11>(a, 0b11111111, a); let e = _mm_set_epi16(0, 1, 2, 3, 7, 6, 6, 4); assert_eq_m128i(r, e); } From cc968bd7f2f8948f6bba802fb211927e2ccd04f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:48:07 +0100 Subject: [PATCH 50/73] convert `_mm_maskz_shufflelo_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 48647ec156..5ae8f1041b 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7273,15 +7273,11 @@ pub unsafe fn _mm_mask_shufflelo_epi16( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_shufflelo_epi16&expand=5214) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpshuflw, imm8 = 5))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm_maskz_shufflelo_epi16(k: __mmask8, a: __m128i, imm8: i32) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_shufflelo_epi16::<$imm8>(a) - }; - } - let shuffle = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpshuflw, IMM8 = 5))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm_maskz_shufflelo_epi16(k: __mmask8, a: __m128i) -> __m128i { + static_assert_imm8!(IMM8); + let shuffle = _mm_shufflelo_epi16::(a); let zero = _mm_setzero_si128().as_i16x8(); transmute(simd_select_bitmask(k, shuffle.as_i16x8(), zero)) } @@ -16376,9 +16372,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm_maskz_shufflelo_epi16() { let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7); - let r = _mm_maskz_shufflelo_epi16(0, a, 0b00_01_01_11); + let r = _mm_maskz_shufflelo_epi16::<0b00_01_01_11>(0, a); assert_eq_m128i(r, _mm_setzero_si128()); - let r = _mm_maskz_shufflelo_epi16(0b11111111, a, 0b00_01_01_11); + let r = _mm_maskz_shufflelo_epi16::<0b00_01_01_11>(0b11111111, a); let e = _mm_set_epi16(0, 1, 2, 3, 7, 6, 6, 4); assert_eq_m128i(r, e); } From 32aa7e6d7f07f0c6973ef908cfa8ccd3f99dd024 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:49:19 +0100 Subject: [PATCH 51/73] convert `_mm512_mask_shufflehi_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 5ae8f1041b..7d70e463da 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7345,20 +7345,15 @@ pub unsafe fn _mm512_shufflehi_epi16(a: __m512i, imm8: i32) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_shufflehi_epi16&expand=5210) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpshufhw, imm8 = 0))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_mask_shufflehi_epi16( +#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 0))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_mask_shufflehi_epi16( src: __m512i, k: __mmask32, a: __m512i, - imm8: i32, ) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_shufflehi_epi16(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm512_shufflehi_epi16(a, IMM8); transmute(simd_select_bitmask(k, r.as_i16x32(), src.as_i16x32())) } @@ -16402,10 +16397,13 @@ mod tests { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, ); - let r = _mm512_mask_shufflehi_epi16(a, 0, a, 0b00_01_01_11); + let r = _mm512_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0, a); assert_eq_m512i(r, a); - let r = - _mm512_mask_shufflehi_epi16(a, 0b11111111_11111111_11111111_11111111, a, 0b00_01_01_11); + let r = _mm512_mask_shufflehi_epi16::<0b00_01_01_11>( + a, + 0b11111111_11111111_11111111_11111111, + a, + ); #[rustfmt::skip] let e = _mm512_set_epi16( 3, 2, 2, 0, 4, 5, 6, 7, 11, 10, 10, 8, 12, 13, 14, 15, From df7f3444eb7856c0a6f9d147cd40797394736d70 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:50:18 +0100 Subject: [PATCH 52/73] convert `_mm512_maskz_shufflehi_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 7d70e463da..847c6b2e65 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7362,15 +7362,11 @@ pub unsafe fn _mm512_mask_shufflehi_epi16( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_shufflehi_epi16&expand=5211) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpshufhw, imm8 = 0))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm512_maskz_shufflehi_epi16(k: __mmask32, a: __m512i, imm8: i32) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_shufflehi_epi16(a, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm512_maskz_shufflehi_epi16(k: __mmask32, a: __m512i) -> __m512i { + static_assert_imm8!(IMM8); + let r = _mm512_shufflehi_epi16(a, IMM8); let zero = _mm512_setzero_si512().as_i16x32(); transmute(simd_select_bitmask(k, r.as_i16x32(), zero)) } @@ -16419,10 +16415,10 @@ mod tests { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, ); - let r = _mm512_maskz_shufflehi_epi16(0, a, 0b00_01_01_11); + let r = _mm512_maskz_shufflehi_epi16::<0b00_01_01_11>(0, a); assert_eq_m512i(r, _mm512_setzero_si512()); let r = - _mm512_maskz_shufflehi_epi16(0b11111111_11111111_11111111_11111111, a, 0b00_01_01_11); + _mm512_maskz_shufflehi_epi16::<0b00_01_01_11>(0b11111111_11111111_11111111_11111111, a); #[rustfmt::skip] let e = _mm512_set_epi16( 3, 2, 2, 0, 4, 5, 6, 7, 11, 10, 10, 8, 12, 13, 14, 15, From ac84cef38893120ed630404b382939fd81553476 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:51:41 +0100 Subject: [PATCH 53/73] convert `_mm256_mask_shufflehi_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 847c6b2e65..fc957f54a9 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7376,20 +7376,15 @@ pub unsafe fn _mm512_maskz_shufflehi_epi16(k: __mmask32, a: __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_shufflehi_epi16&expand=5207) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpshufhw, imm8 = 5))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm256_mask_shufflehi_epi16( +#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm256_mask_shufflehi_epi16( src: __m256i, k: __mmask16, a: __m256i, - imm8: i32, ) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_shufflehi_epi16(a, $imm8) - }; - } - let shuffle = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let shuffle = _mm256_shufflehi_epi16(a, IMM8); transmute(simd_select_bitmask(k, shuffle.as_i16x16(), src.as_i16x16())) } @@ -16430,9 +16425,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm256_mask_shufflehi_epi16() { let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r = _mm256_mask_shufflehi_epi16(a, 0, a, 0b00_01_01_11); + let r = _mm256_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0, a); assert_eq_m256i(r, a); - let r = _mm256_mask_shufflehi_epi16(a, 0b11111111_11111111, a, 0b00_01_01_11); + let r = _mm256_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0b11111111_11111111, a); let e = _mm256_set_epi16(3, 2, 2, 0, 4, 5, 6, 7, 11, 10, 10, 8, 12, 13, 14, 15); assert_eq_m256i(r, e); } From f409f1c7c0f3988179edfc4f9c21e122f84c3739 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:52:25 +0100 Subject: [PATCH 54/73] convert `_mm256_maskz_shufflehi_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index fc957f54a9..c40a0db161 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7393,15 +7393,11 @@ pub unsafe fn _mm256_mask_shufflehi_epi16( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_shufflehi_epi16&expand=5208) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpshufhw, imm8 = 5))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm256_maskz_shufflehi_epi16(k: __mmask16, a: __m256i, imm8: i32) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_shufflehi_epi16(a, $imm8) - }; - } - let shuffle = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm256_maskz_shufflehi_epi16(k: __mmask16, a: __m256i) -> __m256i { + static_assert_imm8!(IMM8); + let shuffle = _mm256_shufflehi_epi16(a, IMM8); let zero = _mm256_setzero_si256().as_i16x16(); transmute(simd_select_bitmask(k, shuffle.as_i16x16(), zero)) } @@ -16435,9 +16431,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm256_maskz_shufflehi_epi16() { let a = _mm256_set_epi16(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r = _mm256_maskz_shufflehi_epi16(0, a, 0b00_01_01_11); + let r = _mm256_maskz_shufflehi_epi16::<0b00_01_01_11>(0, a); assert_eq_m256i(r, _mm256_setzero_si256()); - let r = _mm256_maskz_shufflehi_epi16(0b11111111_11111111, a, 0b00_01_01_11); + let r = _mm256_maskz_shufflehi_epi16::<0b00_01_01_11>(0b11111111_11111111, a); let e = _mm256_set_epi16(3, 2, 2, 0, 4, 5, 6, 7, 11, 10, 10, 8, 12, 13, 14, 15); assert_eq_m256i(r, e); } From 5e14a30b4b466122bdac440e5cb855a344f63dfc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:53:30 +0100 Subject: [PATCH 55/73] convert `_mm_mask_shufflehi_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index c40a0db161..d9d04de63f 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7407,20 +7407,15 @@ pub unsafe fn _mm256_maskz_shufflehi_epi16(k: __mmask16, a: __m /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_shufflehi_epi16&expand=5204) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpshufhw, imm8 = 5))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm_mask_shufflehi_epi16( +#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm_mask_shufflehi_epi16( src: __m128i, k: __mmask8, a: __m128i, - imm8: i32, ) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_shufflehi_epi16::<$imm8>(a) - }; - } - let shuffle = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let shuffle = _mm_shufflehi_epi16::(a); transmute(simd_select_bitmask(k, shuffle.as_i16x8(), src.as_i16x8())) } @@ -16441,9 +16436,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm_mask_shufflehi_epi16() { let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7); - let r = _mm_mask_shufflehi_epi16(a, 0, a, 0b00_01_01_11); + let r = _mm_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0, a); assert_eq_m128i(r, a); - let r = _mm_mask_shufflehi_epi16(a, 0b11111111, a, 0b00_01_01_11); + let r = _mm_mask_shufflehi_epi16::<0b00_01_01_11>(a, 0b11111111, a); let e = _mm_set_epi16(3, 2, 2, 0, 4, 5, 6, 7); assert_eq_m128i(r, e); } From a42603c1a19d4b866a7425ab0dc7e0d576e24be5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:54:29 +0100 Subject: [PATCH 56/73] convert `_mm_maskz_shufflehi_epi16` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index d9d04de63f..24a63bbcb2 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7424,15 +7424,11 @@ pub unsafe fn _mm_mask_shufflehi_epi16( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_shufflehi_epi16&expand=5205) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[cfg_attr(test, assert_instr(vpshufhw, imm8 = 5))] -#[rustc_args_required_const(2)] -pub unsafe fn _mm_maskz_shufflehi_epi16(k: __mmask8, a: __m128i, imm8: i32) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_shufflehi_epi16::<$imm8>(a) - }; - } - let shuffle = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpshufhw, IMM8 = 5))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn _mm_maskz_shufflehi_epi16(k: __mmask8, a: __m128i) -> __m128i { + static_assert_imm8!(IMM8); + let shuffle = _mm_shufflehi_epi16::(a); let zero = _mm_setzero_si128().as_i16x8(); transmute(simd_select_bitmask(k, shuffle.as_i16x8(), zero)) } @@ -16446,9 +16442,9 @@ mod tests { #[simd_test(enable = "avx512bw,avx512vl")] unsafe fn test_mm_maskz_shufflehi_epi16() { let a = _mm_set_epi16(0, 1, 2, 3, 4, 5, 6, 7); - let r = _mm_maskz_shufflehi_epi16(0, a, 0b00_01_01_11); + let r = _mm_maskz_shufflehi_epi16::<0b00_01_01_11>(0, a); assert_eq_m128i(r, _mm_setzero_si128()); - let r = _mm_maskz_shufflehi_epi16(0b11111111, a, 0b00_01_01_11); + let r = _mm_maskz_shufflehi_epi16::<0b00_01_01_11>(0b11111111, a); let e = _mm_set_epi16(3, 2, 2, 0, 4, 5, 6, 7); assert_eq_m128i(r, e); } From 32208c8758fa395dd5b4c8b97e4b80011c455b90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:56:11 +0100 Subject: [PATCH 57/73] convert `_mm512_dbsad_epu8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 24a63bbcb2..fdbde910c7 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7865,17 +7865,13 @@ pub unsafe fn _mm512_sad_epu8(a: __m512i, b: __m512i) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_dbsad_epu8&expand=2114) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vdbpsadbw, imm8 = 0))] -pub unsafe fn _mm512_dbsad_epu8(a: __m512i, b: __m512i, imm8: i32) -> __m512i { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] +pub unsafe fn _mm512_dbsad_epu8(a: __m512i, b: __m512i) -> __m512i { + static_assert_imm8!(IMM8); let a = a.as_u8x64(); let b = b.as_u8x64(); - macro_rules! call { - ($imm8:expr) => { - vdbpsadbw(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vdbpsadbw(a, b, IMM8); transmute(r) } @@ -16870,7 +16866,7 @@ mod tests { unsafe fn test_mm512_dbsad_epu8() { let a = _mm512_set1_epi8(2); let b = _mm512_set1_epi8(4); - let r = _mm512_dbsad_epu8(a, b, 0); + let r = _mm512_dbsad_epu8::<0>(a, b); let e = _mm512_set1_epi16(8); assert_eq_m512i(r, e); } From 3b2f98c9969af6a571de07aa773739d2ad1d3e20 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:57:08 +0100 Subject: [PATCH 58/73] convert `_mm512_mask_dbsad_epu8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index fdbde910c7..e868e00349 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7880,23 +7880,18 @@ pub unsafe fn _mm512_dbsad_epu8(a: __m512i, b: __m512i) -> __m5 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_dbsad_epu8&expand=2115) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(4)] -#[cfg_attr(test, assert_instr(vdbpsadbw, imm8 = 0))] -pub unsafe fn _mm512_mask_dbsad_epu8( +#[rustc_legacy_const_generics(4)] +#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] +pub unsafe fn _mm512_mask_dbsad_epu8( src: __m512i, k: __mmask32, a: __m512i, b: __m512i, - imm8: i32, ) -> __m512i { + static_assert_imm8!(IMM8); let a = a.as_u8x64(); let b = b.as_u8x64(); - macro_rules! call { - ($imm8:expr) => { - vdbpsadbw(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vdbpsadbw(a, b, IMM8); transmute(simd_select_bitmask(k, r, src.as_u16x32())) } @@ -16876,9 +16871,9 @@ mod tests { let src = _mm512_set1_epi16(1); let a = _mm512_set1_epi8(2); let b = _mm512_set1_epi8(4); - let r = _mm512_mask_dbsad_epu8(src, 0, a, b, 0); + let r = _mm512_mask_dbsad_epu8::<0>(src, 0, a, b); assert_eq_m512i(r, src); - let r = _mm512_mask_dbsad_epu8(src, 0b11111111_11111111_11111111_11111111, a, b, 0); + let r = _mm512_mask_dbsad_epu8::<0>(src, 0b11111111_11111111_11111111_11111111, a, b); let e = _mm512_set1_epi16(8); assert_eq_m512i(r, e); } From bff52b58273b7a8d075867841bb2a6f815ccb278 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:58:10 +0100 Subject: [PATCH 59/73] convert `_mm512_maskz_dbsad_epu8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index e868e00349..4247eeb13e 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7900,17 +7900,17 @@ pub unsafe fn _mm512_mask_dbsad_epu8( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_dbsad_epu8&expand=2116) #[inline] #[target_feature(enable = "avx512bw")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vdbpsadbw, imm8 = 0))] -pub unsafe fn _mm512_maskz_dbsad_epu8(k: __mmask32, a: __m512i, b: __m512i, imm8: i32) -> __m512i { +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] +pub unsafe fn _mm512_maskz_dbsad_epu8( + k: __mmask32, + a: __m512i, + b: __m512i, +) -> __m512i { + static_assert_imm8!(IMM8); let a = a.as_u8x64(); let b = b.as_u8x64(); - macro_rules! call { - ($imm8:expr) => { - vdbpsadbw(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vdbpsadbw(a, b, IMM8); transmute(simd_select_bitmask( k, r, @@ -16882,9 +16882,9 @@ mod tests { unsafe fn test_mm512_maskz_dbsad_epu8() { let a = _mm512_set1_epi8(2); let b = _mm512_set1_epi8(4); - let r = _mm512_maskz_dbsad_epu8(0, a, b, 0); + let r = _mm512_maskz_dbsad_epu8::<0>(0, a, b); assert_eq_m512i(r, _mm512_setzero_si512()); - let r = _mm512_maskz_dbsad_epu8(0b11111111_11111111_11111111_11111111, a, b, 0); + let r = _mm512_maskz_dbsad_epu8::<0>(0b11111111_11111111_11111111_11111111, a, b); let e = _mm512_set1_epi16(8); assert_eq_m512i(r, e); } From 31d15ff737464b6387171a9a8dd13f901f44d7a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:58:50 +0100 Subject: [PATCH 60/73] convert `_mm256_dbsad_epu8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 4247eeb13e..49b9864b67 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7923,17 +7923,13 @@ pub unsafe fn _mm512_maskz_dbsad_epu8( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_dbsad_epu8&expand=2111) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vdbpsadbw, imm8 = 0))] -pub unsafe fn _mm256_dbsad_epu8(a: __m256i, b: __m256i, imm8: i32) -> __m256i { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] +pub unsafe fn _mm256_dbsad_epu8(a: __m256i, b: __m256i) -> __m256i { + static_assert_imm8!(IMM8); let a = a.as_u8x32(); let b = b.as_u8x32(); - macro_rules! call { - ($imm8:expr) => { - vdbpsadbw256(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vdbpsadbw256(a, b, IMM8); transmute(r) } @@ -16893,7 +16889,7 @@ mod tests { unsafe fn test_mm256_dbsad_epu8() { let a = _mm256_set1_epi8(2); let b = _mm256_set1_epi8(4); - let r = _mm256_dbsad_epu8(a, b, 0); + let r = _mm256_dbsad_epu8::<0>(a, b); let e = _mm256_set1_epi16(8); assert_eq_m256i(r, e); } From ba5e53614c5c7ed1c425e3140b9dcc281d422299 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 00:59:38 +0100 Subject: [PATCH 61/73] convert `_mm256_mask_dbsad_epu8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 49b9864b67..efcc6fc186 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7938,23 +7938,18 @@ pub unsafe fn _mm256_dbsad_epu8(a: __m256i, b: __m256i) -> __m2 /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_dbsad_epu8&expand=2112) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(4)] -#[cfg_attr(test, assert_instr(vdbpsadbw, imm8 = 0))] -pub unsafe fn _mm256_mask_dbsad_epu8( +#[rustc_legacy_const_generics(4)] +#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] +pub unsafe fn _mm256_mask_dbsad_epu8( src: __m256i, k: __mmask16, a: __m256i, b: __m256i, - imm8: i32, ) -> __m256i { + static_assert_imm8!(IMM8); let a = a.as_u8x32(); let b = b.as_u8x32(); - macro_rules! call { - ($imm8:expr) => { - vdbpsadbw256(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vdbpsadbw256(a, b, IMM8); transmute(simd_select_bitmask(k, r, src.as_u16x16())) } @@ -16899,9 +16894,9 @@ mod tests { let src = _mm256_set1_epi16(1); let a = _mm256_set1_epi8(2); let b = _mm256_set1_epi8(4); - let r = _mm256_mask_dbsad_epu8(src, 0, a, b, 0); + let r = _mm256_mask_dbsad_epu8::<0>(src, 0, a, b); assert_eq_m256i(r, src); - let r = _mm256_mask_dbsad_epu8(src, 0b11111111_11111111, a, b, 0); + let r = _mm256_mask_dbsad_epu8::<0>(src, 0b11111111_11111111, a, b); let e = _mm256_set1_epi16(8); assert_eq_m256i(r, e); } From d93ffb3ea647f02b62f54b4bf8e576fd17e89768 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 01:00:10 +0100 Subject: [PATCH 62/73] convert `_mm256_maskz_dbsad_epu8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index efcc6fc186..a8cf3db3ff 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7958,17 +7958,13 @@ pub unsafe fn _mm256_mask_dbsad_epu8( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_dbsad_epu8&expand=2113) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vdbpsadbw, imm8 = 0))] -pub unsafe fn _mm256_maskz_dbsad_epu8(k: __mmask16, a: __m256i, b: __m256i, imm8: i32) -> __m256i { +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] +pub unsafe fn _mm256_maskz_dbsad_epu8(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { + static_assert_imm8!(IMM8); let a = a.as_u8x32(); let b = b.as_u8x32(); - macro_rules! call { - ($imm8:expr) => { - vdbpsadbw256(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vdbpsadbw256(a, b, IMM8); transmute(simd_select_bitmask( k, r, @@ -16905,9 +16901,9 @@ mod tests { unsafe fn test_mm256_maskz_dbsad_epu8() { let a = _mm256_set1_epi8(2); let b = _mm256_set1_epi8(4); - let r = _mm256_maskz_dbsad_epu8(0, a, b, 0); + let r = _mm256_maskz_dbsad_epu8::<0>(0, a, b); assert_eq_m256i(r, _mm256_setzero_si256()); - let r = _mm256_maskz_dbsad_epu8(0b11111111_11111111, a, b, 0); + let r = _mm256_maskz_dbsad_epu8::<0>(0b11111111_11111111, a, b); let e = _mm256_set1_epi16(8); assert_eq_m256i(r, e); } From 492314e3dd3807271b6c18435981a40ab93c3f2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 01:00:51 +0100 Subject: [PATCH 63/73] convert `_mm_dbsad_epu8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index a8cf3db3ff..b95c73fff7 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7960,7 +7960,11 @@ pub unsafe fn _mm256_mask_dbsad_epu8( #[target_feature(enable = "avx512bw,avx512vl")] #[rustc_legacy_const_generics(3)] #[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] -pub unsafe fn _mm256_maskz_dbsad_epu8(k: __mmask16, a: __m256i, b: __m256i) -> __m256i { +pub unsafe fn _mm256_maskz_dbsad_epu8( + k: __mmask16, + a: __m256i, + b: __m256i, +) -> __m256i { static_assert_imm8!(IMM8); let a = a.as_u8x32(); let b = b.as_u8x32(); @@ -7977,17 +7981,13 @@ pub unsafe fn _mm256_maskz_dbsad_epu8(k: __mmask16, a: __m256i, /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_dbsad_epu8&expand=2108) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(2)] -#[cfg_attr(test, assert_instr(vdbpsadbw, imm8 = 0))] -pub unsafe fn _mm_dbsad_epu8(a: __m128i, b: __m128i, imm8: i32) -> __m128i { +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] +pub unsafe fn _mm_dbsad_epu8(a: __m128i, b: __m128i) -> __m128i { + static_assert_imm8!(IMM8); let a = a.as_u8x16(); let b = b.as_u8x16(); - macro_rules! call { - ($imm8:expr) => { - vdbpsadbw128(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vdbpsadbw128(a, b, IMM8); transmute(r) } @@ -16912,7 +16912,7 @@ mod tests { unsafe fn test_mm_dbsad_epu8() { let a = _mm_set1_epi8(2); let b = _mm_set1_epi8(4); - let r = _mm_dbsad_epu8(a, b, 0); + let r = _mm_dbsad_epu8::<0>(a, b); let e = _mm_set1_epi16(8); assert_eq_m128i(r, e); } From aefa8a762c8e692891a06aed44b8c1c9af7512bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 01:01:56 +0100 Subject: [PATCH 64/73] convert `_mm_mask_dbsad_epu8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index b95c73fff7..034cdb8745 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -7996,23 +7996,18 @@ pub unsafe fn _mm_dbsad_epu8(a: __m128i, b: __m128i) -> __m128i /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_dbsad_epu8&expand=2109) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(4)] -#[cfg_attr(test, assert_instr(vdbpsadbw, imm8 = 0))] -pub unsafe fn _mm_mask_dbsad_epu8( +#[rustc_legacy_const_generics(4)] +#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] +pub unsafe fn _mm_mask_dbsad_epu8( src: __m128i, k: __mmask8, a: __m128i, b: __m128i, - imm8: i32, ) -> __m128i { + static_assert_imm8!(IMM8); let a = a.as_u8x16(); let b = b.as_u8x16(); - macro_rules! call { - ($imm8:expr) => { - vdbpsadbw128(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vdbpsadbw128(a, b, IMM8); transmute(simd_select_bitmask(k, r, src.as_u16x8())) } @@ -16922,9 +16917,9 @@ mod tests { let src = _mm_set1_epi16(1); let a = _mm_set1_epi8(2); let b = _mm_set1_epi8(4); - let r = _mm_mask_dbsad_epu8(src, 0, a, b, 0); + let r = _mm_mask_dbsad_epu8::<0>(src, 0, a, b); assert_eq_m128i(r, src); - let r = _mm_mask_dbsad_epu8(src, 0b11111111, a, b, 0); + let r = _mm_mask_dbsad_epu8::<0>(src, 0b11111111, a, b); let e = _mm_set1_epi16(8); assert_eq_m128i(r, e); } From 2f96bad995dea8edd223182b493b9c690fcba0a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 01:02:34 +0100 Subject: [PATCH 65/73] convert `_mm_maskz_dbsad_epu8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 034cdb8745..d0dee28c95 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -8016,17 +8016,17 @@ pub unsafe fn _mm_mask_dbsad_epu8( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_dbsad_epu8&expand=2110) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vdbpsadbw, imm8 = 0))] -pub unsafe fn _mm_maskz_dbsad_epu8(k: __mmask8, a: __m128i, b: __m128i, imm8: i32) -> __m128i { +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vdbpsadbw, IMM8 = 0))] +pub unsafe fn _mm_maskz_dbsad_epu8( + k: __mmask8, + a: __m128i, + b: __m128i, +) -> __m128i { + static_assert_imm8!(IMM8); let a = a.as_u8x16(); let b = b.as_u8x16(); - macro_rules! call { - ($imm8:expr) => { - vdbpsadbw128(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + let r = vdbpsadbw128(a, b, IMM8); transmute(simd_select_bitmask(k, r, _mm_setzero_si128().as_u16x8())) } @@ -16928,9 +16928,9 @@ mod tests { unsafe fn test_mm_maskz_dbsad_epu8() { let a = _mm_set1_epi8(2); let b = _mm_set1_epi8(4); - let r = _mm_maskz_dbsad_epu8(0, a, b, 0); + let r = _mm_maskz_dbsad_epu8::<0>(0, a, b); assert_eq_m128i(r, _mm_setzero_si128()); - let r = _mm_maskz_dbsad_epu8(0b11111111, a, b, 0); + let r = _mm_maskz_dbsad_epu8::<0>(0b11111111, a, b); let e = _mm_set1_epi16(8); assert_eq_m128i(r, e); } From 602125bb99c968c3dc86315d4019f08990152158 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 01:04:24 +0100 Subject: [PATCH 66/73] convert `_mm512_mask_alignr_epi8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index d0dee28c95..0b7e564eb4 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -9056,21 +9056,16 @@ pub unsafe fn _mm512_alignr_epi8(a: __m512i, b: __m512i, imm8: i32) -> __m512i { /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_alignr_epi8&expand=264) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpalignr, imm8 = 1))] -#[rustc_args_required_const(4)] -pub unsafe fn _mm512_mask_alignr_epi8( +#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))] +#[rustc_legacy_const_generics(4)] +pub unsafe fn _mm512_mask_alignr_epi8( src: __m512i, k: __mmask64, a: __m512i, b: __m512i, - imm8: i32, ) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_alignr_epi8(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm512_alignr_epi8(a, b, IMM8); transmute(simd_select_bitmask(k, r.as_i8x64(), src.as_i8x64())) } @@ -17705,14 +17700,13 @@ mod tests { 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, ); let b = _mm512_set1_epi8(1); - let r = _mm512_mask_alignr_epi8(a, 0, a, b, 14); + let r = _mm512_mask_alignr_epi8::<14>(a, 0, a, b); assert_eq_m512i(r, a); - let r = _mm512_mask_alignr_epi8( + let r = _mm512_mask_alignr_epi8::<14>( a, 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111, a, b, - 14, ); #[rustfmt::skip] let e = _mm512_set_epi8( From fe659e28cefa98faa4c667282df6ddfbbc47b397 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 01:06:07 +0100 Subject: [PATCH 67/73] convert `_mm512_maskz_alignr_epi8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 0b7e564eb4..6438b7196b 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -9074,15 +9074,15 @@ pub unsafe fn _mm512_mask_alignr_epi8( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_alignr_epi8&expand=265) #[inline] #[target_feature(enable = "avx512bw")] -#[cfg_attr(test, assert_instr(vpalignr, imm8 = 1))] -#[rustc_args_required_const(3)] -pub unsafe fn _mm512_maskz_alignr_epi8(k: __mmask64, a: __m512i, b: __m512i, imm8: i32) -> __m512i { - macro_rules! call { - ($imm8:expr) => { - _mm512_alignr_epi8(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 1))] +#[rustc_legacy_const_generics(3)] +pub unsafe fn _mm512_maskz_alignr_epi8( + k: __mmask64, + a: __m512i, + b: __m512i, +) -> __m512i { + static_assert_imm8!(IMM8); + let r = _mm512_alignr_epi8(a, b, IMM8); let zero = _mm512_setzero_si512().as_i8x64(); transmute(simd_select_bitmask(k, r.as_i8x64(), zero)) } @@ -17728,13 +17728,12 @@ mod tests { 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, ); let b = _mm512_set1_epi8(1); - let r = _mm512_maskz_alignr_epi8(0, a, b, 14); + let r = _mm512_maskz_alignr_epi8::<14>(0, a, b); assert_eq_m512i(r, _mm512_setzero_si512()); - let r = _mm512_maskz_alignr_epi8( + let r = _mm512_maskz_alignr_epi8::<14>( 0b11111111_11111111_11111111_11111111_11111111_11111111_11111111_11111111, a, b, - 14, ); #[rustfmt::skip] let e = _mm512_set_epi8( From 2da8026da2364696151f5a3ac9e5e1e1df75144c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 01:07:00 +0100 Subject: [PATCH 68/73] convert `_mm256_mask_alignr_epi8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 6438b7196b..82c138abf2 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -9092,21 +9092,16 @@ pub unsafe fn _mm512_maskz_alignr_epi8( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_alignr_epi8&expand=261) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(4)] -#[cfg_attr(test, assert_instr(vpalignr, imm8 = 5))] -pub unsafe fn _mm256_mask_alignr_epi8( +#[rustc_legacy_const_generics(4)] +#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))] +pub unsafe fn _mm256_mask_alignr_epi8( src: __m256i, k: __mmask32, a: __m256i, b: __m256i, - imm8: i32, ) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_alignr_epi8(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm256_alignr_epi8(a, b, IMM8); transmute(simd_select_bitmask(k, r.as_i8x32(), src.as_i8x32())) } @@ -17753,9 +17748,9 @@ mod tests { 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, ); let b = _mm256_set1_epi8(1); - let r = _mm256_mask_alignr_epi8(a, 0, a, b, 14); + let r = _mm256_mask_alignr_epi8::<14>(a, 0, a, b); assert_eq_m256i(r, a); - let r = _mm256_mask_alignr_epi8(a, 0b11111111_11111111_11111111_11111111, a, b, 14); + let r = _mm256_mask_alignr_epi8::<14>(a, 0b11111111_11111111_11111111_11111111, a, b); #[rustfmt::skip] let e = _mm256_set_epi8( 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, From cc1337ab07c2a33ff5527825449ed7b8883ed9f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 01:08:32 +0100 Subject: [PATCH 69/73] convert `_mm256_maskz_alignr_epi8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index 82c138abf2..ccf30f9d96 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -9110,15 +9110,15 @@ pub unsafe fn _mm256_mask_alignr_epi8( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_alignr_epi8&expand=262) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpalignr, imm8 = 5))] -pub unsafe fn _mm256_maskz_alignr_epi8(k: __mmask32, a: __m256i, b: __m256i, imm8: i32) -> __m256i { - macro_rules! call { - ($imm8:expr) => { - _mm256_alignr_epi8(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))] +pub unsafe fn _mm256_maskz_alignr_epi8( + k: __mmask32, + a: __m256i, + b: __m256i, +) -> __m256i { + static_assert_imm8!(IMM8); + let r = _mm256_alignr_epi8(a, b, IMM8); transmute(simd_select_bitmask( k, r.as_i8x32(), @@ -17767,9 +17767,9 @@ mod tests { 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, ); let b = _mm256_set1_epi8(1); - let r = _mm256_maskz_alignr_epi8(0, a, b, 14); + let r = _mm256_maskz_alignr_epi8::<14>(0, a, b); assert_eq_m256i(r, _mm256_setzero_si256()); - let r = _mm256_maskz_alignr_epi8(0b11111111_11111111_11111111_11111111, a, b, 14); + let r = _mm256_maskz_alignr_epi8::<14>(0b11111111_11111111_11111111_11111111, a, b); #[rustfmt::skip] let e = _mm256_set_epi8( 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, From 54e3f6415bd92d9ea71808b1c60bf7d6bcf1b5a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 01:09:23 +0100 Subject: [PATCH 70/73] convert `_mm_mask_alignr_epi8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index ccf30f9d96..a98c445f38 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -9131,21 +9131,16 @@ pub unsafe fn _mm256_maskz_alignr_epi8( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_alignr_epi8&expand=258) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(4)] -#[cfg_attr(test, assert_instr(vpalignr, imm8 = 5))] -pub unsafe fn _mm_mask_alignr_epi8( +#[rustc_legacy_const_generics(4)] +#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))] +pub unsafe fn _mm_mask_alignr_epi8( src: __m128i, k: __mmask16, a: __m128i, b: __m128i, - imm8: i32, ) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_alignr_epi8(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); + static_assert_imm8!(IMM8); + let r = _mm_alignr_epi8(a, b, IMM8); transmute(simd_select_bitmask(k, r.as_i8x16(), src.as_i8x16())) } @@ -17782,9 +17777,9 @@ mod tests { unsafe fn test_mm_mask_alignr_epi8() { let a = _mm_set_epi8(1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0); let b = _mm_set1_epi8(1); - let r = _mm_mask_alignr_epi8(a, 0, a, b, 14); + let r = _mm_mask_alignr_epi8::<14>(a, 0, a, b); assert_eq_m128i(r, a); - let r = _mm_mask_alignr_epi8(a, 0b11111111_11111111, a, b, 14); + let r = _mm_mask_alignr_epi8::<14>(a, 0b11111111_11111111, a, b); let e = _mm_set_epi8(0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1); assert_eq_m128i(r, e); } From d5bcabad9bc9e4dd3fe1e469eb8daa6914f42b6b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 01:10:25 +0100 Subject: [PATCH 71/73] convert `_mm_maskz_alignr_epi8` to const generics --- crates/core_arch/src/x86/avx512bw.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/avx512bw.rs b/crates/core_arch/src/x86/avx512bw.rs index a98c445f38..2128a828ff 100644 --- a/crates/core_arch/src/x86/avx512bw.rs +++ b/crates/core_arch/src/x86/avx512bw.rs @@ -9149,15 +9149,15 @@ pub unsafe fn _mm_mask_alignr_epi8( /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_alignr_epi8&expand=259) #[inline] #[target_feature(enable = "avx512bw,avx512vl")] -#[rustc_args_required_const(3)] -#[cfg_attr(test, assert_instr(vpalignr, imm8 = 5))] -pub unsafe fn _mm_maskz_alignr_epi8(k: __mmask16, a: __m128i, b: __m128i, imm8: i32) -> __m128i { - macro_rules! call { - ($imm8:expr) => { - _mm_alignr_epi8(a, b, $imm8) - }; - } - let r = constify_imm8_sae!(imm8, call); +#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(vpalignr, IMM8 = 5))] +pub unsafe fn _mm_maskz_alignr_epi8( + k: __mmask16, + a: __m128i, + b: __m128i, +) -> __m128i { + static_assert_imm8!(IMM8); + let r = _mm_alignr_epi8(a, b, IMM8); let zero = _mm_setzero_si128().as_i8x16(); transmute(simd_select_bitmask(k, r.as_i8x16(), zero)) } @@ -17788,9 +17788,9 @@ mod tests { unsafe fn test_mm_maskz_alignr_epi8() { let a = _mm_set_epi8(1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0); let b = _mm_set1_epi8(1); - let r = _mm_maskz_alignr_epi8(0, a, b, 14); + let r = _mm_maskz_alignr_epi8::<14>(0, a, b); assert_eq_m128i(r, _mm_setzero_si128()); - let r = _mm_maskz_alignr_epi8(0b11111111_11111111, a, b, 14); + let r = _mm_maskz_alignr_epi8::<14>(0b11111111_11111111, a, b); let e = _mm_set_epi8(0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1); assert_eq_m128i(r, e); } From 050d981e561fb42f28fc5fc820b6953ea563cb00 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Thu, 4 Mar 2021 21:44:53 +0100 Subject: [PATCH 72/73] convert `_xabort` to const generics --- crates/core_arch/src/x86/rtm.rs | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/crates/core_arch/src/x86/rtm.rs b/crates/core_arch/src/x86/rtm.rs index 7cb1cc09bd..dab73cde9e 100644 --- a/crates/core_arch/src/x86/rtm.rs +++ b/crates/core_arch/src/x86/rtm.rs @@ -76,15 +76,11 @@ pub unsafe fn _xend() { /// [Intel's documentation](https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-xabort). #[inline] #[target_feature(enable = "rtm")] -#[cfg_attr(test, assert_instr(xabort, imm8 = 0x0))] -#[rustc_args_required_const(0)] -pub unsafe fn _xabort(imm8: u32) { - macro_rules! call { - ($imm8:expr) => { - x86_xabort($imm8) - }; - } - constify_imm8!(imm8, call) +#[cfg_attr(test, assert_instr(xabort, IMM8 = 0x0))] +#[rustc_legacy_const_generics(0)] +pub unsafe fn _xabort() { + static_assert_imm_u8!(IMM8); + x86_xabort(IMM8 as i8) } /// Queries whether the processor is executing in a transactional region identified by restricted @@ -130,14 +126,14 @@ mod tests { unsafe fn test_xabort() { const ABORT_CODE: u32 = 42; // aborting outside a transactional region does nothing - _xabort(ABORT_CODE); + _xabort::(); for _ in 0..10 { let mut x = 0; let code = rtm::_xbegin(); if code == _XBEGIN_STARTED { x += 1; - rtm::_xabort(ABORT_CODE); + rtm::_xabort::(); } else if code & _XABORT_EXPLICIT != 0 { let test_abort_code = rtm::_xabort_code(code); assert_eq!(test_abort_code, ABORT_CODE); From 18b5cef59b6622481862d707d3913ca3676d16ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=A9my=20Rakic?= Date: Fri, 5 Mar 2021 03:56:21 +0100 Subject: [PATCH 73/73] temporarily disable WASM CI The LLVM12 upgrade in rustc may be causing issues --- .github/workflows/main.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index c7cec5a858..615a121b7a 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -77,7 +77,7 @@ jobs: - mips64-unknown-linux-gnuabi64 - mips64el-unknown-linux-gnuabi64 - s390x-unknown-linux-gnu - - wasm32-wasi + # - wasm32-wasi - i586-unknown-linux-gnu - x86_64-linux-android - arm-linux-androideabi @@ -131,8 +131,8 @@ jobs: disable_assert_instr: true - target: s390x-unknown-linux-gnu os: ubuntu-latest - - target: wasm32-wasi - os: ubuntu-latest + # - target: wasm32-wasi + # os: ubuntu-latest - target: aarch64-apple-darwin os: macos-latest norun: true