riscv: implement non-pow2 indirect loads

Author: Rexicon226

src/arch/riscv64/CodeGen.zig

@@ -6855,10 +6855,10 @@ fn genSetReg(func: *Func, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
                     else => return std.debug.panic("TODO: genSetReg for float size {d}", .{abi_size}),
                 },
                 .int => switch (abi_size) {
-                    1 => .lb,
-                    2 => .lh,
-                    4 => .lw,
-                    8 => .ld,
+                    1...1 => .lb,
+                    2...2 => .lh,
+                    3...4 => .lw,
+                    5...8 => .ld,
                     else => return std.debug.panic("TODO: genSetReg for int size {d}", .{abi_size}),
                 },
                 .vector => {

test/behavior/defer.zig

@@ -94,7 +94,6 @@ test "mixing normal and error defers" {
     if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
-    if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
 
     try expect(runSomeErrorDefers(true) catch unreachable);
     try expect(result[0] == 'c');