[CHERI-RISCV] Inline expansion of capability-based cmpxchg in hybrid mode#490

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arichardson wants to merge 8 commits intoCTSRD-CHERI:devfrom arichardson:hybrid-atomics-part2

Commits on Aug 15, 2022

[CHERI-RISC-V] Swap CheriStoreCond_r operand order to match AMO_rr
arichardson
committed
[CHERI-RISC-V] Fix capability i8/i16 cmpxchg in hybrid mode
arichardson
committed
[CHERI-RISC-V] Handle capability-based cmpxchg in hybrid mode
arichardson
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[CHERI-RISC-V] Fix lowering of i8/i16 cmpxchg using a capability pointer
arichardson
committed
[CHERI-Generic] Add cmpxchg tests with all memory order combinations
arichardson
committed
[CHERI-RISC-V] Insert the required fences for explicit address mode atomics
arichardson
committed
[CHERI-RISC-V] Support capability-based integer atomic RMW ops
arichardson
committed
[CHERI-RISC-V] Expand capability AtomicRMW XCHG in hybrid mode
arichardson
committed