Deoptimize TLS access #17800
Deoptimize TLS access #17800
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* Apparently `ifunc` is not supported by gcc 5 on ARM * Try even harder to workaround LLVM bug when dealing with returntwice function
yuyichao
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| // It's also harder to emit the offset in a generic way on AArch64 | ||
| // (need to generate one or two `add` with shift) so let llvm emit | ||
| // the add for now. | ||
| auto T_size = (sizeof(size_t) == 8 ? Type::getInt64Ty(ctx) : |
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are there aarch64 variants without 8 byte pointers?
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This line is moved here from the above and I'm keeping it as close as possible to what it used to be with the hope that the LLVM bug can be fixed and we can revert all these workarounds.
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Can we merge this? julia seems very unstable right now. |
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I got the clobber list wrong the first time so I'd like someone else familiar with x86 asm to double check. Should be good to go otherwise (especially since we've branched). |
| // The add instruction clobbers flags | ||
| auto tp = InlineAsm::get(FunctionType::get(T_pint8, false), | ||
| asm_str.c_str(), | ||
| "=r,~{dirflag},~{fpsr},~{flags}", false); |
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why does this clobber the fpu status register? also, afaict, dirflags is deprecated and a no-op
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Mainly because this is what clang generates and I couldn't find a single documentation of what each one mean and can't really figure out the logic in the x86 target code that uses these flags..
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lgtm |
Apparently
ifuncis not supported by gcc 5 on ARMWorkaround Build still fails on Raspberry Pi 3 #17264 (comment)
Try even harder to workaround LLVM bug when dealing with returntwice function
Workaround New segfault when tests fail with --inline=no #17793