RISCV: Add some definitions and vararg supports

src/core/stdc/stdarg.d

@@ -47,6 +47,8 @@ version (MIPS32)  version = MIPS_Any;
 version (MIPS64)  version = MIPS_Any;
 version (PPC)     version = PPC_Any;
 version (PPC64)   version = PPC_Any;
+version (RISCV32) version = RISCV_Any;
+version (RISCV64) version = RISCV_Any;
 
 version (GNU)
 {
@@ -130,6 +132,12 @@ else version (AAPCS64)
 {
     alias va_list = core.internal.vararg.aarch64.va_list;
 }
+else version (RISCV_Any)
+{
+    // The va_list type is void*, according to RISCV Calling Convention
+    // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
+    alias va_list = void*;
+}
 else
 {
     alias va_list = char*; // incl. unknown platforms
@@ -259,6 +267,12 @@ T va_arg(T)(ref va_list ap)
         ap += T.sizeof.alignUp;
         return *p;
     }
+    else version (RISCV_Any)
+    {
+        auto p = cast(T*) ap;
+        ap += T.sizeof.alignUp;
+        return *p;
+    }
     else
         static assert(0, "Unsupported platform");
 }

src/core/sys/elf/package.d

@@ -2510,3 +2510,66 @@ enum R_TILEGX_GNU_VTINHERIT =  128;
 enum R_TILEGX_GNU_VTENTRY =    129;
 
 enum R_TILEGX_NUM =            130;
+
+enum EF_RISCV_RVC =              0x0001;
+enum EF_RISCV_FLOAT_ABI =        0x0006;
+enum EF_RISCV_FLOAT_ABI_SOFT =   0x0000;
+enum EF_RISCV_FLOAT_ABI_SINGLE = 0x0002;
+enum EF_RISCV_FLOAT_ABI_DOUBLE = 0x0004;
+enum EF_RISCV_FLOAT_ABI_QUAD =   0x0006;
+enum R_RISCV_NONE =            0;
+enum R_RISCV_32 =              1;
+enum R_RISCV_64 =              2;
+enum R_RISCV_RELATIVE =        3;
+enum R_RISCV_COPY =            4;
+enum R_RISCV_JUMP_SLOT =       5;
+enum R_RISCV_TLS_DTPMOD32 =    6;
+enum R_RISCV_TLS_DTPMOD64 =    7;
+enum R_RISCV_TLS_DTPREL32 =    8;
+enum R_RISCV_TLS_DTPREL64 =    9;
+enum R_RISCV_TLS_TPREL32 =     10;
+enum R_RISCV_TLS_TPREL64 =     11;
+enum R_RISCV_BRANCH =          16;
+enum R_RISCV_JAL =             17;
+enum R_RISCV_CALL =            18;
+enum R_RISCV_CALL_PLT =        19;
+enum R_RISCV_GOT_HI20 =        20;
+enum R_RISCV_TLS_GOT_HI20 =    21;
+enum R_RISCV_TLS_GD_HI20 =     22;
+enum R_RISCV_PCREL_HI20 =      23;
+enum R_RISCV_PCREL_LO12_I =    24;
+enum R_RISCV_PCREL_LO12_S =    25;
+enum R_RISCV_HI20 =            26;
+enum R_RISCV_LO12_I =          27;
+enum R_RISCV_LO12_S =          28;
+enum R_RISCV_TPREL_HI20 =      29;
+enum R_RISCV_TPREL_LO12_I =    30;
+enum R_RISCV_TPREL_LO12_S =    31;
+enum R_RISCV_TPREL_ADD =       32;
+enum R_RISCV_ADD8 =            33;
+enum R_RISCV_ADD16 =           34;
+enum R_RISCV_ADD32 =           35;
+enum R_RISCV_ADD64 =           36;
+enum R_RISCV_SUB8 =            37;
+enum R_RISCV_SUB16 =           38;
+enum R_RISCV_SUB32 =           39;
+enum R_RISCV_SUB64 =           40;
+enum R_RISCV_GNU_VTINHERIT =   41;
+enum R_RISCV_GNU_VTENTRY =     42;
+enum R_RISCV_ALIGN =           43;
+enum R_RISCV_RVC_BRANCH =      44;
+enum R_RISCV_RVC_JUMP =        45;
+enum R_RISCV_RVC_LUI =         46;
+enum R_RISCV_GPREL_I =         47;
+enum R_RISCV_GPREL_S =         48;
+enum R_RISCV_TPREL_I =         49;
+enum R_RISCV_TPREL_S =         50;
+enum R_RISCV_RELAX =           51;
+enum R_RISCV_SUB6 =            52;
+enum R_RISCV_SET6 =            53;
+enum R_RISCV_SET8 =            54;
+enum R_RISCV_SET16 =           55;
+enum R_RISCV_SET32 =           56;
+enum R_RISCV_32_PCREL =        57;
+enum R_RISCV_IRELATIVE =       58;
+enum R_RISCV_NUM =             59;

src/core/sys/posix/fcntl.d

@@ -123,6 +123,12 @@ version (linux)
     enum F_SETLK        = 6;
     enum F_SETLKW       = 7;
   }
+  else version (RISCV64)
+  {
+    enum F_GETLK        = 5;
+    enum F_SETLK        = 6;
+    enum F_SETLKW       = 7;
+  }
   else version (SystemZ)
   {
     static assert(off_t.sizeof == 8);

src/core/vararg.d

@@ -28,6 +28,8 @@ version (MIPS32)  version = MIPS_Any;
 version (MIPS64)  version = MIPS_Any;
 version (PPC)     version = PPC_Any;
 version (PPC64)   version = PPC_Any;
+version (RISCV32) version = RISCV_Any;
+version (RISCV64) version = RISCV_Any;
 
 version (ARM_Any)
 {
@@ -136,6 +138,13 @@ void va_arg()(ref va_list ap, TypeInfo ti, void* parmn)
         ap += tsize.alignUp;
         parmn[0..tsize] = p[0..tsize];
     }
+    else version (RISCV_Any)
+    {
+        const tsize = ti.tsize;
+        auto p = cast(void*) ap;
+        ap += tsize.alignUp;
+        parmn[0..tsize] = p[0..tsize];
+    }
     else
         static assert(0, "Unsupported platform");
 }

src/rt/dwarfeh.d

@@ -73,6 +73,16 @@ else version (MIPS32)
     enum eh_exception_regno = 4;
     enum eh_selector_regno = 5;
 }
+else version (RISCV64)
+{
+    enum eh_exception_regno = 10;
+    enum eh_selector_regno = 11;
+}
+else version (RISCV32)
+{
+    enum eh_exception_regno = 10;
+    enum eh_selector_regno = 11;
+}
 else
 {
     static assert(0, "Unknown EH register numbers for this architecture");