PHY8720(A) init timout failures: need to revert "GPIO refactoring (#6259)"

[dok-net]

The PR #6259 mentioned in this PR's subject line, broke the PHY8720(A). There have been a few issues posted regarding the timeouts. I have performed a git bisect to identify the offended PR, and reduced it to the lines that need to be considered for revert or otherwise, how the absense of this special mode handling causes the failure and where exactly would be the proper place to implement this oversight, after all. I am afraid I don't have the resources to hack the IDF, too.

#5239
#6500
#6142
#5993

[github-actions]

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[me-no-dev]

@dok-net this is a very good find! But let's fix it properly by editing ETH.cpp instead :)

Replacing all pinMode(pin, FUNCTION_x) here with direct register access instead. Here is the block edited:

    if(eth_clock_mode == ETH_CLOCK_GPIO0_IN){
#ifndef CONFIG_ETH_RMII_CLK_INPUT
        // RMII clock (50MHz) input to GPIO0
        //gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_EMAC_TX_CLK);
        //PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[0]);
        pinMode(0, INPUT);
        PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[0], 5);
        EMAC_EXT.ex_clk_ctrl.ext_en = 1;
        EMAC_EXT.ex_clk_ctrl.int_en = 0;
        EMAC_EXT.ex_oscclk_conf.clk_sel = 1;
#endif
    } else {
        if(eth_clock_mode == ETH_CLOCK_GPIO0_OUT){
#ifndef CONFIG_ETH_RMII_CLK_OUTPUT_GPIO0
            // APLL clock output to GPIO0 (must be configured to 50MHz!)
            //gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
            //PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[0]);
            pinMode(0, OUTPUT);
            PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[0], 1);
            // Choose the APLL clock to output on GPIO
            REG_WRITE(PIN_CTRL, 6);
#endif
        } else if(eth_clock_mode == ETH_CLOCK_GPIO16_OUT){
#if CONFIG_ETH_RMII_CLK_OUT_GPIO != 16
            // RMII CLK (50MHz) output to GPIO16
            //gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
            //PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[16]);
            pinMode(16, OUTPUT);
            PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[16], 5);
#endif
        } else if(eth_clock_mode == ETH_CLOCK_GPIO17_OUT){
#if CONFIG_ETH_RMII_CLK_OUT_GPIO != 17
            // RMII CLK (50MHz) output to GPIO17
            //gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_GPIO17_U, FUNC_GPIO17_EMAC_CLK_OUT_180);
            //PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[17]);
            pinMode(17, OUTPUT);
            PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[17], 5);
#endif
        }

[dok-net]

SPECIAL isn't used anymore, anyway, right?

[me-no-dev]

SPECIAL isn't used anymore, anyway, right?

Not used anymore (since we switched GPIO to IDF)

[me-no-dev]

Thanks @dok-net ! Now merged!

[Jason2866]

Removing

#define SPECIAL           0xF0
#define FUNCTION_1        0x00
#define FUNCTION_2        0x20
#define FUNCTION_3        0x40
#define FUNCTION_4        0x60
#define FUNCTION_5        0x80
#define FUNCTION_6        0xA0
#define ANALOG            0xC0

is a uneeded breaking change. It can brake existing code and Librarys without no need.
one example https://github.com/earlephilhower/ESP8266Audio
I will open a PR to revert this change.

[me-no-dev]

it is needed. lib needs updating. This no longer works

[dok-net]

@Jason2866 If you must know :-)
Since #6259, https://github.com/Xinyuan-LilyGO/LilyGO-T-ETH-POE no longer worked, the PHY setup timed out.