tock · gendx · Apr 21, 2020 · Apr 21, 2020 · Apr 21, 2020 · Apr 21, 2020
diff --git a/.travis.yml b/.travis.yml
@@ -35,7 +35,7 @@ os:
 # If you change this, you must also change Getting_Started.md, Makefile.common,
 # .vscode/settings.json, and tools/netlify-build.sh.
 rust:
-  - nightly-2020-03-06
+  - nightly-2020-04-21
 
 before_script:
   - npm install -g markdown-toc

diff --git a/.vscode/settings.json b/.vscode/settings.json
@@ -1,4 +1,4 @@
 {
     "editor.formatOnSave": true,
-    "rust-client.channel": "nightly-2020-03-06",
+    "rust-client.channel": "nightly-2020-04-21",
 }
diff --git a/arch/cortex-m/src/lib.rs b/arch/cortex-m/src/lib.rs
@@ -2,7 +2,7 @@
 
 #![crate_name = "cortexm"]
 #![crate_type = "rlib"]
-#![feature(asm, lang_items)]
+#![feature(llvm_asm, lang_items)]
 #![no_std]
 
 use core::fmt::Write;

diff --git a/arch/cortex-m/src/support.rs b/arch/cortex-m/src/support.rs
@@ -5,15 +5,15 @@ use core::ops::FnOnce;
 /// NOP instruction
 pub fn nop() {
     unsafe {
-        asm!("nop" :::: "volatile");
+        llvm_asm!("nop" :::: "volatile");
     }
 }
 
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[inline(always)]
 /// WFI instruction
 pub unsafe fn wfi() {
-    asm!("wfi" :::: "volatile");
+    llvm_asm!("wfi" :::: "volatile");
 }
 
 #[cfg(all(target_arch = "arm", target_os = "none"))]
@@ -22,12 +22,12 @@ where
     F: FnOnce() -> R,
 {
     // Set PRIMASK
-    asm!("cpsid i" :::: "volatile");
+    llvm_asm!("cpsid i" :::: "volatile");
 
     let res = f();
 
     // Unset PRIMASK
-    asm!("cpsie i" :::: "volatile");
+    llvm_asm!("cpsie i" :::: "volatile");
     return res;
 }
 

diff --git a/arch/cortex-m0/src/lib.rs b/arch/cortex-m0/src/lib.rs
@@ -2,7 +2,7 @@
 
 #![crate_name = "cortexm0"]
 #![crate_type = "rlib"]
-#![feature(asm, core_intrinsics, naked_functions)]
+#![feature(llvm_asm, core_intrinsics, naked_functions)]
 #![no_std]
 
 // Re-export the base generic cortex-m functions here as they are
@@ -35,7 +35,7 @@ pub unsafe extern "C" fn generic_isr() {
 #[naked]
 /// All ISRs are caught by this handler which disables the NVIC and switches to the kernel.
 pub unsafe extern "C" fn generic_isr() {
-    asm!(
+    llvm_asm!(
         "
     /* Skip saving process state if not coming from user-space */
     ldr r0, MEXC_RETURN_PSP
@@ -111,7 +111,7 @@ pub unsafe extern "C" fn svc_handler() {
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[naked]
 pub unsafe extern "C" fn svc_handler() {
-    asm!(
+    llvm_asm!(
         "
   ldr r0, EXC_RETURN_MSP
   cmp lr, r0
@@ -150,7 +150,7 @@ pub unsafe extern "C" fn switch_to_user(
     mut user_stack: *const u8,
     process_regs: &mut [usize; 8],
 ) -> *mut u8 {
-    asm!("
+    llvm_asm!("
     /* Load non-hardware-stacked registers from Process stack */
     ldmia $2!, {r4-r7}
     mov r11, r7
@@ -226,7 +226,7 @@ unsafe fn kernel_hardfault(faulting_stack: *mut u32) {
     //       value. Therefore as a workaround, capture the stacked
     //       registers and invoke a breakpoint.
     //
-    asm!("
+    llvm_asm!("
          bkpt
 1:
          b 1b
@@ -251,7 +251,7 @@ pub unsafe extern "C" fn hard_fault_handler() {
 
     // If `kernel_stack` is non-zero, then hard-fault occurred in
     // kernel, otherwise the hard-fault occurrend in user.
-    asm!("
+    llvm_asm!("
     /*
      * Will be incremented to 1 when we determine that it was a fault
      * in the kernel
@@ -287,7 +287,7 @@ _hardfault_exit:
     } else {
         // hard fault occurred in an app, not the kernel. The app should be
         // marked as in an error state and handled by the kernel
-        asm!("
+        llvm_asm!("
              ldr r0, =APP_HARD_FAULT
              movs r1, #1 /* Fault */
              str r1, [r0, #0]

diff --git a/arch/cortex-m3/src/lib.rs b/arch/cortex-m3/src/lib.rs
@@ -2,7 +2,7 @@
 
 #![crate_name = "cortexm3"]
 #![crate_type = "rlib"]
-#![feature(asm, core_intrinsics, naked_functions)]
+#![feature(llvm_asm, core_intrinsics, naked_functions)]
 #![no_std]
 
 pub mod mpu;
@@ -38,7 +38,7 @@ pub unsafe extern "C" fn systick_handler() {
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[naked]
 pub unsafe extern "C" fn systick_handler() {
-    asm!(
+    llvm_asm!(
         "
     /* Mark that the systick handler was called meaning that the process */
     /* stopped executing because it has exceeded its timeslice. */
@@ -65,7 +65,7 @@ pub unsafe extern "C" fn generic_isr() {
 #[naked]
 /// All ISRs are caught by this handler which disables the NVIC and switches to the kernel.
 pub unsafe extern "C" fn generic_isr() {
-    asm!(
+    llvm_asm!(
         "
     /* Skip saving process state if not coming from user-space */
     cmp lr, #0xfffffffd
@@ -130,7 +130,7 @@ pub unsafe extern "C" fn svc_handler() {
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[naked]
 pub unsafe extern "C" fn svc_handler() {
-    asm!(
+    llvm_asm!(
         "
     cmp lr, #0xfffffff9
     bne to_kernel
@@ -173,7 +173,7 @@ pub unsafe extern "C" fn switch_to_user(
     mut user_stack: *const usize,
     process_regs: &mut [usize; 8],
 ) -> *const usize {
-    asm!("
+    llvm_asm!("
     /* Load bottom of stack into Process Stack Pointer */
     msr psp, $0
 
@@ -353,7 +353,7 @@ pub unsafe extern "C" fn hard_fault_handler() {
     let faulting_stack: *mut u32;
     let kernel_stack: bool;
 
-    asm!(
+    llvm_asm!(
     "mov    r1, 0                       \n\
      tst    lr, #4                      \n\
      itte   eq                          \n\
@@ -371,7 +371,7 @@ pub unsafe extern "C" fn hard_fault_handler() {
     } else {
         // hard fault occurred in an app, not the kernel. The app should be
         //  marked as in an error state and handled by the kernel
-        asm!(
+        llvm_asm!(
             "ldr r0, =APP_HARD_FAULT
               mov r1, #1 /* Fault */
               str r1, [r0, #0]

diff --git a/arch/cortex-m4/src/lib.rs b/arch/cortex-m4/src/lib.rs
@@ -2,7 +2,7 @@
 
 #![crate_name = "cortexm4"]
 #![crate_type = "rlib"]
-#![feature(asm, core_intrinsics, naked_functions)]
+#![feature(llvm_asm, core_intrinsics, naked_functions)]
 #![no_std]
 
 pub mod mpu;
@@ -41,7 +41,7 @@ pub unsafe extern "C" fn systick_handler() {
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[naked]
 pub unsafe extern "C" fn systick_handler() {
-    asm!(
+    llvm_asm!(
         "
     // Mark that the systick handler was called meaning that the process stopped
     // executing because it has exceeded its timeslice. This is a global
@@ -81,7 +81,7 @@ pub unsafe extern "C" fn generic_isr() {
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[naked]
 pub unsafe extern "C" fn generic_isr() {
-    asm!(
+    llvm_asm!(
         "
     // Set thread mode to privileged to ensure we are executing as the kernel.
     // This may be redundant if the interrupt happened while the kernel code
@@ -152,7 +152,7 @@ pub unsafe extern "C" fn svc_handler() {
 #[cfg(all(target_arch = "arm", target_os = "none"))]
 #[naked]
 pub unsafe extern "C" fn svc_handler() {
-    asm!(
+    llvm_asm!(
         "
     // First check to see which direction we are going in. If the link register
     // is something other than 0xfffffff9, then we are coming from an app which
@@ -209,7 +209,7 @@ pub unsafe extern "C" fn switch_to_user(
     mut user_stack: *const usize,
     process_regs: &mut [usize; 8],
 ) -> *const usize {
-    asm!(
+    llvm_asm!(
         "
     // The arguments passed in are:
     // - `r0` is the top of the user stack
@@ -400,7 +400,7 @@ pub unsafe extern "C" fn hard_fault_handler() {
     let faulting_stack: *mut u32;
     let kernel_stack: bool;
 
-    asm!(
+    llvm_asm!(
      "/* Read the SCB registers. */
      ldr r0, =SCB_REGISTERS
      ldr r1, =0xE000ED14
@@ -432,7 +432,7 @@ pub unsafe extern "C" fn hard_fault_handler() {
     } else {
         // hard fault occurred in an app, not the kernel. The app should be
         //  marked as in an error state and handled by the kernel
-        asm!(
+        llvm_asm!(
             "ldr r0, =APP_HARD_FAULT
               mov r1, #1 /* Fault */
               str r1, [r0, #0]

diff --git a/arch/rv32i/src/lib.rs b/arch/rv32i/src/lib.rs
@@ -3,7 +3,7 @@
 #![crate_name = "rv32i"]
 #![crate_type = "rlib"]
 #![feature(
-    asm,
+    llvm_asm,
     const_fn,
     lang_items,
     global_asm,
@@ -50,7 +50,7 @@ extern "C" {
 #[naked]
 pub extern "C" fn _start() {
     unsafe {
-        asm! ("
+        llvm_asm! ("
             // Set the global pointer register using the variable defined in the
             // linker script. This register is only set once. The global pointer
             // is a method for sharing state between the linker and the CPU so
@@ -155,7 +155,7 @@ pub extern "C" fn _start_trap() {
 #[naked]
 pub extern "C" fn _start_trap() {
     unsafe {
-        asm! ("
+        llvm_asm! ("
             // The first thing we have to do is determine if we came from user
             // mode or kernel mode, as we need to save state and proceed
             // differently. We cannot, however, use any registers because we do
@@ -341,7 +341,7 @@ pub extern "C" fn _start_trap() {
 #[export_name = "abort"]
 pub extern "C" fn abort() {
     unsafe {
-        asm! ("
+        llvm_asm! ("
             // Simply go back to the start as if we had just booted.
             j    _start
         "

diff --git a/arch/rv32i/src/support.rs b/arch/rv32i/src/support.rs
@@ -8,15 +8,15 @@ use core::ops::FnOnce;
 /// NOP instruction
 pub fn nop() {
     unsafe {
-        asm!("nop" :::: "volatile");
+        llvm_asm!("nop" :::: "volatile");
     }
 }
 
 #[cfg(all(target_arch = "riscv32", target_os = "none"))]
 #[inline(always)]
 /// WFI instruction
 pub unsafe fn wfi() {
-    asm!("wfi" :::: "volatile");
+    llvm_asm!("wfi" :::: "volatile");
 }
 
 pub unsafe fn atomic<F, R>(f: F) -> R

diff --git a/arch/rv32i/src/syscall.rs b/arch/rv32i/src/syscall.rs
@@ -125,7 +125,7 @@ impl kernel::syscall::UserspaceKernelBoundary for SysCall {
         _stack_pointer: *const usize,
         state: &mut RiscvimacStoredState,
     ) -> (*mut usize, ContextSwitchReason) {
-        asm! ("
+        llvm_asm! ("
           // Before switching to the app we need to save the kernel registers to
           // the kernel stack. We then save the stack pointer in the mscratch
           // CSR (0x340) so we can retrieve it after returning to the kernel

diff --git a/boards/hifive1/src/main.rs b/boards/hifive1/src/main.rs
@@ -10,7 +10,7 @@
 
 #![no_std]
 #![no_main]
-#![feature(asm)]
+#![feature(llvm_asm)]
 
 use capsules::virtual_alarm::{MuxAlarm, VirtualMuxAlarm};
 use kernel::capabilities;

diff --git a/boards/nucleo_f429zi/src/main.rs b/boards/nucleo_f429zi/src/main.rs
@@ -4,7 +4,7 @@
 
 #![no_std]
 #![no_main]
-#![feature(asm)]
+#![feature(llvm_asm)]
 #![deny(missing_docs)]
 
 use capsules::virtual_alarm::VirtualMuxAlarm;

diff --git a/boards/nucleo_f446re/src/main.rs b/boards/nucleo_f446re/src/main.rs
@@ -4,7 +4,7 @@
 
 #![no_std]
 #![no_main]
-#![feature(asm)]
+#![feature(llvm_asm)]
 #![deny(missing_docs)]
 
 use capsules::virtual_alarm::VirtualMuxAlarm;

diff --git a/boards/opentitan/src/main.rs b/boards/opentitan/src/main.rs
@@ -4,7 +4,7 @@
 
 #![no_std]
 #![no_main]
-#![feature(asm)]
+#![feature(llvm_asm)]
 
 use capsules::virtual_alarm::{MuxAlarm, VirtualMuxAlarm};
 use kernel::capabilities;

diff --git a/boards/stm32f3discovery/src/main.rs b/boards/stm32f3discovery/src/main.rs
@@ -4,7 +4,7 @@
 
 #![no_std]
 #![no_main]
-#![feature(asm, core_intrinsics)]
+#![feature(llvm_asm, core_intrinsics)]
 #![deny(missing_docs)]
 
 use capsules::virtual_alarm::VirtualMuxAlarm;

diff --git a/chips/arty_e21_chip/src/chip.rs b/chips/arty_e21_chip/src/chip.rs
@@ -42,7 +42,7 @@ impl ArtyExx {
     /// used later as needed.
     #[cfg(all(target_arch = "riscv32", target_os = "none"))]
     pub unsafe fn disable_machine_timer(&self) {
-        asm!("
+        llvm_asm!("
             // Initialize machine timer mtimecmp to disable the machine timer
             // interrupt.
             li   t0, -1       // Set mtimecmp to 0xFFFFFFFF
@@ -70,7 +70,7 @@ impl ArtyExx {
     /// valid for platforms with a CLIC.
     #[cfg(all(target_arch = "riscv32", target_os = "none"))]
     pub unsafe fn configure_trap_handler(&self) {
-        asm!("
+        llvm_asm!("
             // The csrw instruction writes a Control and Status Register (CSR)
             // with a new value.
             //
@@ -189,7 +189,7 @@ pub extern "C" fn start_trap_rust() {
     let mut mcause: i32;
 
     unsafe {
-        asm!("
+        llvm_asm!("
             // Read the mcause CSR to determine why we entered the trap handler.
             // Since we are using the CLIC, the hardware includes the interrupt
             // index in the mcause register.

diff --git a/chips/arty_e21_chip/src/lib.rs b/chips/arty_e21_chip/src/lib.rs
@@ -1,6 +1,6 @@
 //! Drivers and chip support for the E21 soft core.
 
-#![feature(asm)]
+#![feature(llvm_asm)]
 #![no_std]
 #![crate_name = "arty_e21_chip"]
 #![crate_type = "rlib"]

diff --git a/chips/e310x/src/lib.rs b/chips/e310x/src/lib.rs
@@ -1,6 +1,6 @@
 //! Chip support for the E310 from SiFive.
 
-#![feature(asm)]
+#![feature(llvm_asm)]
 #![no_std]
 #![crate_name = "e310x"]
 #![crate_type = "rlib"]